mirror of
https://github.com/hrydgard/ppsspp.git
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Merge latest arm emitters from Sonic1's work.
This commit is contained in:
Henrik Rydgard
parent
de309f6a8b
commit
c1338259bc
@ -78,11 +78,25 @@ bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated)
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}
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}
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void ARMXEmitter::MOVI2R(ARMReg reg, u32 val)
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void ARMXEmitter::MOVI2R(ARMReg reg, u32 val, bool optimize)
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{
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Operand2 op2;
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bool inverse;
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if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) {
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if (!optimize)
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{
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// Only used in backpatch atm
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// Only support ARMv7 right now
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if (cpu_info.bArmV7) {
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MOVW(reg, val & 0xFFFF);
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MOVT(reg, val, true);
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}
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else
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{
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// ARMv6 version won't use backpatch for now
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// Run again with optimizations
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MOVI2R(reg, val);
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}
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} else if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) {
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if (!inverse)
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MOV(reg, op2);
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else
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@ -115,7 +129,14 @@ void ARMXEmitter::MOVI2R(ARMReg reg, u32 val)
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}
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}
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}
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// Moves IMM to memory location
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void ARMXEmitter::ARMABI_MOVI2M(Operand2 op, Operand2 val)
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{
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// This moves imm to a memory location
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MOVW(R14, val); MOVT(R14, val, true);
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MOVW(R12, op); MOVT(R12, op, true);
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STR(R12, R14); // R10 is what we want to store
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}
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void ARMXEmitter::QuickCallFunction(ARMReg reg, void *func) {
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MOVI2R(reg, (u32)(func));
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BL(reg);
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@ -404,7 +425,7 @@ void ARMXEmitter::MOVT(ARMReg Rd, Operand2 Rm, bool TopBits) { WriteInstruction(
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void ARMXEmitter::WriteInstruction (u32 Op, ARMReg Rd, ARMReg Rn, Operand2 Rm, bool SetFlags) // This can get renamed later
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{
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u32 op = InstOps[Op][Rm.GetType()]; // Type always decided by last operand
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s32 op = InstOps[Op][Rm.GetType()]; // Type always decided by last operand
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u32 Data = Rm.GetData();
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if (Rm.GetType() == TYPE_IMM)
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{
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@ -419,7 +440,7 @@ void ARMXEmitter::WriteInstruction (u32 Op, ARMReg Rd, ARMReg Rn, Operand2 Rm, b
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break;
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}
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}
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if (op == (u32)-1)
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if (op == -1)
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_assert_msg_(DYNA_REC, false, "%s not yet support %d", InstNames[Op], Rm.GetType());
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Write32(condition | (op << 21) | (SetFlags ? (1 << 20) : 0) | Rn << 16 | Rd << 12 | Data);
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}
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@ -486,6 +507,10 @@ void ARMXEmitter::REV (ARMReg dest, ARMReg src )
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{
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Write32(condition | (107 << 20) | (15 << 16) | (dest << 12) | (243 << 4) | src);
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}
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void ARMXEmitter::REV16(ARMReg dest, ARMReg src)
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{
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Write32(condition | (0x3DF << 16) | (dest << 12) | (0xFD << 4) | src);
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}
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void ARMXEmitter::_MSR (bool write_nzcvq, bool write_g, Operand2 op2)
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{
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@ -526,8 +551,17 @@ void ARMXEmitter::DMB ()
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{
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Write32(0xF57FF05E);
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}
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void ARMXEmitter::SVC(Operand2 op)
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{
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Write32(condition | (0x0F << 24) | op.Imm24());
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}
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void ARMXEmitter::LDR (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x41, src, dest, op);}
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void ARMXEmitter::LDRH(ARMReg dest, ARMReg src, Operand2 op)
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{
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u8 Imm = op.Imm8();
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Write32(condition | (0x05 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
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}
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void ARMXEmitter::LDRB(ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x45, src, dest, op);}
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void ARMXEmitter::LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
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@ -569,19 +603,249 @@ void ARMXEmitter::LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...)
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WriteRegStoreOp(0x89, dest, WriteBack, RegList);
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}
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// NEON and ASIMD
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ARMReg ARMXEmitter::SubBase(ARMReg Reg)
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{
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if (Reg >= S0)
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{
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if (Reg >= D0)
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{
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if (Reg >= Q0)
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return (ARMReg)((Reg - Q0) * 2); // Always gets encoded as a double register
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return (ARMReg)(Reg - D0);
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}
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return (ARMReg)(Reg - S0);
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}
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return Reg;
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}
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// NEON Specific
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void ARMXEmitter::VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= Q0, "Pass invalid register to VADD(integer)");
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_assert_msg_(DYNA_REC, cpu_info.bNEON, "Can't use VADD(integer) when CPU doesn't support it");
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// Gets encoded as a double register
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | (Size << 20) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0x8 << 8) | ((Vn & 0x10) << 3) | (1 << 6) \
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| ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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void ARMXEmitter::VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= Q0, "Pass invalid register to VSUB(integer)");
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_assert_msg_(DYNA_REC, cpu_info.bNEON, "Can't use VSUB(integer) when CPU doesn't support it");
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// Gets encoded as a double register
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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Write32((0xF3 << 24) | ((Vd & 0x10) << 18) | (Size << 20) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0x8 << 8) | ((Vn & 0x10) << 3) | (1 << 6) \
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| ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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// VFP Specific
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void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, Operand2 op)
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{
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_assert_msg_(DYNA_REC, Dest >= S0 && Dest <= D31, "Passed Invalid dest register to VLDR");
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_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid Base register to VLDR");
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_assert_msg_(DYNA_REC, !(op.Imm12() & 4), "Offset needs to be word aligned");
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bool single_reg = Dest < D0;
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Dest = SubBase(Dest);
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if (single_reg)
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Dest = (ARMReg)(Dest - S0);
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{
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Write32(NO_COND | (0x1B << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
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| ((Dest & 0x1E) << 11) | (10 << 8) | (op.Imm12() >> 2));
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}
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else
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Dest = (ARMReg)(Dest - D0);
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Write32(NO_COND | (13 << 24) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
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| (5 << 9) | (!single_reg << 8) | op.Imm8());
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{
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Write32(NO_COND | (0x1B << 23) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
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| ((Dest & 0xF) << 12) | (11 << 8) | (op.Imm12() >> 2));
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}
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}
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void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, Operand2 op)
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{
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_assert_msg_(DYNA_REC, Src >= S0 && Src <= D31, "Passed invalid src register to VSTR");
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_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid base register to VSTR");
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_assert_msg_(DYNA_REC, !(op.Imm12() & 4), "Offset needs to be word aligned");
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bool single_reg = Src < D0;
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Src = SubBase(Src);
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if (single_reg)
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{
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Write32(NO_COND | (0x1B << 23) | ((Src & 0x1) << 22) | (Base << 16) \
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| ((Src & 0x1E) << 11) | (10 << 8) | (op.Imm12() >> 2));
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}
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else
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{
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Write32(NO_COND | (0x1B << 23) | ((Src & 0x10) << 18) | (Base << 16) \
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| ((Src & 0xF) << 12) | (11 << 8) | (op.Imm12() >> 2));
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}
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}
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void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \
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| (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \
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| (0x2F << 6) | ((Vm & 0x10) << 1) | (Vm & 0xF));
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}
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}
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void ARMXEmitter::VCMP(ARMReg Vd)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \
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| (0x2B << 6));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \
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| (0x2F << 6));
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}
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}
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void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Pased invalid dest register to VSQRT");
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_assert_msg_(DYNA_REC, Vn < Q0, "Passed invalid Vn to VSQRT");
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_assert_msg_(DYNA_REC, Vm < Q0, "Passed invalid Vm to VSQRT");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | ((Vn & 0x1E) << 16) \
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| ((Vd & 0x1E) << 11) | (0xA << 8) | ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) \
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| (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0xB << 8) | ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) \
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| (Vm & 0xF));
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}
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}
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void ARMXEmitter::VSQRT(ARMReg Vd, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd < Q0, "Pased invalid dest register to VSQRT");
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_assert_msg_(DYNA_REC, Vm < Q0, "Passed invalid Vm to VSQRT");
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bool single_reg = Vd < D0;
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Vd = SubBase(Vd);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
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| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
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| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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// VFP and ASIMD
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void ARMXEmitter::VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VADD");
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_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VADD");
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_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VADD");
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bool single_reg = Vd < D0;
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bool double_reg = Vd < Q0;
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 12) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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if (double_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
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| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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else
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{
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_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
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Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3) \
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| (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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}
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void ARMXEmitter::VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm)
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{
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_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VSUB");
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_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VSUB");
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_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VSUB");
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bool single_reg = Vd < D0;
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bool double_reg = Vd < Q0;
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Vd = SubBase(Vd);
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Vn = SubBase(Vn);
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Vm = SubBase(Vm);
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if (single_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
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| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 12) | (0x5 << 9) \
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| ((Vn & 0x1) << 7) | (1 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
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}
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else
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{
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if (double_reg)
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{
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Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
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| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
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| ((Vn & 0x10) << 3) | (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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else
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{
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_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
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Write32((0xF2 << 24) | (1 << 21) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
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| ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3) \
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| (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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}
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}
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void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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{
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if (Dest > R15)
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@ -600,6 +864,7 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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{
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// Move 64bit from Arm reg
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_assert_msg_(DYNA_REC, false, "This VMOV doesn't support moving 64bit ARM to NEON");
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return;
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}
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}
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}
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@ -613,13 +878,13 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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Src = (ARMReg)(Src - S0);
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Write32(NO_COND | (0xE1 << 20) | ((Src & 0x1E) << 15) | (Dest << 12) \
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| (0xA << 8) | ((Src & 0x1) << 7) | (1 << 4));
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return;
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}
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else
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{
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// Move 64bit To Arm reg
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_assert_msg_(DYNA_REC, false, "This VMOV doesn't support moving 64bit ARM From NEON");
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return;
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}
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}
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else
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@ -632,32 +897,35 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
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int SrcSize = Src < D0 ? 1 : Src < Q0 ? 2 : 4;
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int DestSize = Dest < D0 ? 1 : Dest < Q0 ? 2 : 4;
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bool Single = DestSize == 1;
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bool Quad = DestSize == 4;
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_assert_msg_(DYNA_REC, SrcSize == DestSize, "VMOV doesn't support moving different register sizes");
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Dest = SubBase(Dest);
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Src = SubBase(Src);
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if (Single)
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{
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Dest = (ARMReg)(Dest - S0);
|
||||
Src = (ARMReg)(Src - S0);
|
||||
Write32(NO_COND | (0x1D << 23) | ((Dest & 0x1) << 22) | (0x3 << 20) | ((Dest & 0x1E) << 11) \
|
||||
| (0x5 << 9) | (1 << 6) | ((Src & 0x1) << 5) | ((Src & 0x1E) >> 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
// Double and quad
|
||||
bool Quad = DestSize == 4;
|
||||
if (Quad)
|
||||
{
|
||||
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use quad registers when you don't support ASIMD.");
|
||||
// Gets encoded as a Double register
|
||||
Dest = (ARMReg)((Dest - Q0) * 2);
|
||||
Src = (ARMReg)((Src - Q0) * 2);
|
||||
Write32((0xF2 << 24) | ((Dest & 0x10) << 18) | (2 << 20) | ((Src & 0xF) << 16) \
|
||||
| ((Dest & 0xF) << 12) | (1 << 8) | ((Src & 0x10) << 3) | (1 << 6) \
|
||||
| ((Src & 0x10) << 1) | (1 << 4) | (Src & 0xF));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
Dest = (ARMReg)(Dest - D0);
|
||||
Src = (ARMReg)(Src - D0);
|
||||
Write32(NO_COND | (0x1D << 23) | ((Dest & 0x10) << 18) | (0x3 << 20) | ((Dest & 0xF) << 12) \
|
||||
| (0x2D << 6) | ((Src & 0x10) << 1) | (Src & 0xF));
|
||||
}
|
||||
Write32((0xF2 << 24) | ((Dest & 0x10) << 18) | (1 << 21) | ((Src & 0xF) << 16) \
|
||||
| ((Dest & 0xF) << 12) | (1 << 8) | ((Src & 0x10) << 3) | (Quad << 6) \
|
||||
| ((Src & 0x10) << 1) | (1 << 4) | (Src & 0xF));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -97,6 +97,13 @@ enum ShiftType
|
||||
ST_ROR = 3,
|
||||
ST_RRX = 4
|
||||
};
|
||||
enum IntegerSize
|
||||
{
|
||||
I_I8 = 0,
|
||||
I_I16,
|
||||
I_I32,
|
||||
I_I64
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
@ -309,6 +316,9 @@ bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated);
|
||||
inline Operand2 R(ARMReg Reg) { return Operand2(Reg, TYPE_REG); }
|
||||
inline Operand2 IMM(u32 Imm) { return Operand2(Imm, TYPE_IMM); }
|
||||
inline Operand2 Mem(void *ptr) { return Operand2((u32)ptr, TYPE_IMM); }
|
||||
//usage: struct {int e;} s; STRUCT_OFFSET(s,e)
|
||||
#define STRUCT_OFF(str,elem) ((u32)((u32)&(str).elem-(u32)&(str)))
|
||||
|
||||
|
||||
struct FixupBranch
|
||||
{
|
||||
@ -418,6 +428,7 @@ public:
|
||||
void SBC (ARMReg dest, ARMReg src, Operand2 op2);
|
||||
void SBCS(ARMReg dest, ARMReg src, Operand2 op2);
|
||||
void REV (ARMReg dest, ARMReg src);
|
||||
void REV16 (ARMReg dest, ARMReg src);
|
||||
void RSC (ARMReg dest, ARMReg src, Operand2 op2);
|
||||
void RSCS(ARMReg dest, ARMReg src, Operand2 op2);
|
||||
void TST ( ARMReg src, Operand2 op2);
|
||||
@ -459,6 +470,7 @@ public:
|
||||
void LDR (ARMReg dest, ARMReg src, Operand2 op2 = 0);
|
||||
// Offset adds to the base register in LDR
|
||||
void LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
|
||||
void LDRH(ARMReg dest, ARMReg src, Operand2 op = 0);
|
||||
void LDRB(ARMReg dest, ARMReg src, Operand2 op2 = 0);
|
||||
void STR (ARMReg dest, ARMReg src, Operand2 op2 = 0);
|
||||
// Offset adds on to the destination register in STR
|
||||
@ -473,23 +485,37 @@ public:
|
||||
// dest contains the result if the instruction managed to store the value
|
||||
void STREX(ARMReg dest, ARMReg base, ARMReg op);
|
||||
void DMB ();
|
||||
void SVC(Operand2 op);
|
||||
|
||||
// NEON and ASIMD instructions
|
||||
// None of these will be created with conditional since ARM
|
||||
// is deprecating conditional execution of ASIMD instructions.
|
||||
// Some ASIMD instructions don't even have a conditional encoding.
|
||||
// ASIMD instructions don't even have a conditional encoding.
|
||||
|
||||
// Subtracts the base from the register to give us the real one
|
||||
ARMReg SubBase(ARMReg Reg);
|
||||
// NEON Only
|
||||
void VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
|
||||
void VLDR(ARMReg dest, ARMReg Base, Operand2 op);
|
||||
// VFP Only
|
||||
void VLDR(ARMReg Dest, ARMReg Base, Operand2 op);
|
||||
void VSTR(ARMReg Src, ARMReg Base, Operand2 op);
|
||||
void VCMP(ARMReg Vd, ARMReg Vm);
|
||||
// Compares against zero
|
||||
void VCMP(ARMReg Vd);
|
||||
void VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VSQRT(ARMReg Vd, ARMReg Vm);
|
||||
|
||||
// NEON and VFP
|
||||
void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
||||
void VMOV(ARMReg Dest, ARMReg Src);
|
||||
|
||||
void QuickCallFunction(ARMReg scratchreg, void *func);
|
||||
// Utility functions
|
||||
void MOVI2R(ARMReg reg, u32 val);
|
||||
void ARMABI_ShowConditions();
|
||||
void ARMABI_Return();
|
||||
|
||||
void UpdateAPSR(bool NZCVQ, u8 Flags, bool GE, u8 GEval);
|
||||
|
||||
void MOVI2R(ARMReg reg, u32 val, bool optimize = true);
|
||||
void ARMABI_MOVI2M(Operand2 op, Operand2 val);
|
||||
}; // class ARMXEmitter
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user