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https://github.com/hrydgard/ppsspp.git
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ARM64: Port over some missing VFPU instructions from ARM. Not much left now.
This commit is contained in:
Henrik Rydgard
parent
f06e9a9d18
commit
ca58f322e5
@ -3280,12 +3280,12 @@ void ARM64XEmitter::ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
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}
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}
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void ARM64XEmitter::ORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch) {
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void ARM64XEmitter::ORRI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch) {
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unsigned int n, imm_s, imm_r;
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if (IsImmLogical(imm, Is64Bit(Rn) ? 64 : 32, &n, &imm_s, &imm_r)) {
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ORR(Rd, Rn, imm_r, imm_s, n);
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} else {
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_assert_msg_(JIT, scratch != INVALID_REG, "ORI2R - failed to construct immediate value from %08x, need scratch", (u32)imm);
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_assert_msg_(JIT, scratch != INVALID_REG, "ORRI2R - failed to construct immediate value from %08x, need scratch", (u32)imm);
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MOVI2R(scratch, imm);
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ORR(Rd, Rn, scratch);
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}
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@ -691,7 +691,7 @@ public:
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void ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void TSTI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG) { ANDSI2R(Is64Bit(Rn) ? ZR : WZR, Rn, imm, scratch); }
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void ORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void ORRI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void EORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void CMPI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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@ -28,3 +28,8 @@ enum CCFlags
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};
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const u32 NO_COND = 0xE0000000;
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inline CCFlags InvertCond(CCFlags fl) {
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int x = (int)fl;
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x ^= 1;
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return (CCFlags)x;
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}
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@ -1195,13 +1195,233 @@ namespace MIPSComp
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}
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void Arm64Jit::Comp_Vcmp(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix())
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DISABLE;
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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VCondition cond = (VCondition)(op & 0xF);
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u8 sregs[4], tregs[4];
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixT(tregs, sz, _VT);
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// Some, we just fall back to the interpreter.
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// ES is just really equivalent to (value & 0x7F800000) == 0x7F800000.
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switch (cond) {
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case VC_EI: // c = my_isinf(s[i]); break;
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case VC_NI: // c = !my_isinf(s[i]); break;
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DISABLE;
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case VC_ES: // c = my_isnan(s[i]) || my_isinf(s[i]); break; // Tekken Dark Resurrection
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case VC_NS: // c = !my_isnan(s[i]) && !my_isinf(s[i]); break;
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case VC_EN: // c = my_isnan(s[i]); break;
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case VC_NN: // c = !my_isnan(s[i]); break;
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if (_VS != _VT)
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DISABLE;
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break;
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case VC_EZ:
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case VC_NZ:
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break;
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default:
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;
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}
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// First, let's get the trivial ones.
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int affected_bits = (1 << 4) | (1 << 5); // 4 and 5
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MOVI2R(SCRATCH1, 0);
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for (int i = 0; i < n; ++i) {
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// Let's only handle the easy ones, and fall back on the interpreter for the rest.
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CCFlags flag = CC_AL;
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switch (cond) {
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case VC_FL: // c = 0;
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break;
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case VC_TR: // c = 1
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if (i == 0) {
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if (n == 1) {
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MOVI2R(SCRATCH1, 0x31);
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} else {
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MOVI2R(SCRATCH1, 1 << i);
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}
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} else {
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ORRI2R(SCRATCH1, SCRATCH1, 1 << i);
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}
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break;
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case VC_ES: // c = my_isnan(s[i]) || my_isinf(s[i]); break; // Tekken Dark Resurrection
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case VC_NS: // c = !(my_isnan(s[i]) || my_isinf(s[i])); break;
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// For these, we use the integer ALU as there is no support on ARM for testing for INF.
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// Testing for nan or inf is the same as testing for &= 0x7F800000 == 0x7F800000.
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// We need an extra temporary register so we store away SCRATCH1.
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STR(INDEX_UNSIGNED, SCRATCH1, CTXREG, offsetof(MIPSState, temp));
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fpr.MapRegV(sregs[i], 0);
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MOVI2R(SCRATCH1, 0x7F800000);
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fp.FMOV(SCRATCH2, fpr.V(sregs[i]));
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AND(SCRATCH2, SCRATCH2, SCRATCH1);
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CMP(SCRATCH2, SCRATCH1); // (SCRATCH2 & 0x7F800000) == 0x7F800000
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flag = cond == VC_ES ? CC_EQ : CC_NEQ;
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LDR(INDEX_UNSIGNED, SCRATCH1, CTXREG, offsetof(MIPSState, temp));
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break;
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case VC_EN: // c = my_isnan(s[i]); break; // Tekken 6
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// Should we involve T? Where I found this used, it compared a register with itself so should be fine.
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_VS; // overflow = unordered : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdhcfbc.html
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break;
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case VC_NN: // c = !my_isnan(s[i]); break;
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// Should we involve T? Where I found this used, it compared a register with itself so should be fine.
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_VC; // !overflow = !unordered : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdhcfbc.html
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break;
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case VC_EQ: // c = s[i] == t[i]
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_EQ;
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break;
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case VC_LT: // c = s[i] < t[i]
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_LO;
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break;
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case VC_LE: // c = s[i] <= t[i];
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_LS;
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break;
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case VC_NE: // c = s[i] != t[i]
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_NEQ;
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break;
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case VC_GE: // c = s[i] >= t[i]
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_GE;
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break;
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case VC_GT: // c = s[i] > t[i]
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fpr.MapInInV(sregs[i], tregs[i]);
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fp.FCMP(fpr.V(sregs[i]), fpr.V(tregs[i]));
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flag = CC_GT;
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break;
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case VC_EZ: // c = s[i] == 0.0f || s[i] == -0.0f
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fpr.MapRegV(sregs[i]);
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fp.FCMP(fpr.V(sregs[i])); // vcmp(sregs[i], #0.0)
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flag = CC_EQ;
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break;
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case VC_NZ: // c = s[i] != 0
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fpr.MapRegV(sregs[i]);
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fp.FCMP(fpr.V(sregs[i])); // vcmp(sregs[i], #0.0)
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flag = CC_NEQ;
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break;
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default:
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DISABLE;
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}
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if (flag != CC_AL) {
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FixupBranch b = B(InvertCond(flag));
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if (i == 0) {
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if (n == 1) {
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MOVI2R(SCRATCH1, 0x31);
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} else {
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MOVI2R(SCRATCH1, 1); // 1 << i, but i == 0
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}
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} else {
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ORRI2R(SCRATCH1, SCRATCH1, 1 << i);
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}
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SetJumpTarget(b);
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}
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affected_bits |= 1 << i;
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}
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// Aggregate the bits. Urgh, expensive. Can optimize for the case of one comparison, which is the most common
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// after all.
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if (n > 1) {
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CMP(SCRATCH1, affected_bits & 0xF);
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FixupBranch skip1 = B(CC_NEQ);
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ORRI2R(SCRATCH1, SCRATCH1, 1 << 5);
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SetJumpTarget(skip1);
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CMP(SCRATCH1, 0);
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FixupBranch skip2 = B(CC_EQ);
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ORRI2R(SCRATCH1, SCRATCH1, 1 << 4);
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SetJumpTarget(skip2);
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}
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gpr.MapReg(MIPS_REG_VFPUCC, MAP_DIRTY);
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ANDI2R(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), ~affected_bits);
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ORR(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), SCRATCH1);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_Vcmov(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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u8 sregs[4], dregs[4];
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixD(dregs, sz, _VD);
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int tf = (op >> 19) & 1;
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int imm3 = (op >> 16) & 7;
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for (int i = 0; i < n; ++i) {
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// Simplification: Disable if overlap unsafe
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if (!IsOverlapSafeAllowS(dregs[i], i, n, sregs)) {
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DISABLE;
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}
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}
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if (imm3 < 6) {
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// Test one bit of CC. This bit decides whether none or all subregisters are copied.
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fpr.MapRegsAndSpillLockV(dregs, sz, MAP_DIRTY);
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fpr.MapRegsAndSpillLockV(sregs, sz, 0);
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gpr.MapReg(MIPS_REG_VFPUCC);
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TSTI2R(gpr.R(MIPS_REG_VFPUCC), 1 << imm3);
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// TODO: Use fsel?
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FixupBranch b = B(tf ? CC_NEQ : CC_EQ);
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for (int i = 0; i < n; i++) {
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fp.FMOV(fpr.V(dregs[i]), fpr.V(sregs[i]));
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}
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SetJumpTarget(b);
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} else {
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// Look at the bottom four bits of CC to individually decide if the subregisters should be copied.
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fpr.MapRegsAndSpillLockV(dregs, sz, MAP_DIRTY);
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fpr.MapRegsAndSpillLockV(sregs, sz, 0);
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gpr.MapReg(MIPS_REG_VFPUCC);
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for (int i = 0; i < n; i++) {
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TSTI2R(gpr.R(MIPS_REG_VFPUCC), 1 << i);
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FixupBranch b = B(tf ? CC_NEQ : CC_EQ);
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fp.FMOV(fpr.V(dregs[i]), fpr.V(sregs[i]));
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SetJumpTarget(b);
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}
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}
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ApplyPrefixD(dregs, sz);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_Viim(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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@ -1303,7 +1523,7 @@ namespace MIPSComp
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// Very heavily used by FF:CC. Should be replaced by a fast approximation instead of
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// calling the math library.
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void Arm64Jit::Comp_VRot(MIPSOpcode op) {
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DISABLE;
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DISABLE; // Need to figure out how to deal with the return values from the function.
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// VRot probably doesn't accept prefixes anyway.
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CONDITIONAL_DISABLE;
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@ -1343,7 +1563,6 @@ namespace MIPSComp
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bool negSin1 = (imm & 0x10) ? true : false;
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fpr.MapRegV(sreg);
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// We should write a custom pure-asm function instead.
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fp.FMOV(S0, fpr.V(sreg));
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QuickCallFunction(SCRATCH2_64, negSin1 ? (void *)&SinCosNegSin : (void *)&SinCos);
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CompVrotShuffle(dregs, imm, sz, false);
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@ -1362,9 +1581,50 @@ namespace MIPSComp
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}
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void Arm64Jit::Comp_Vocp(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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u8 sregs[4], dregs[4];
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// Actually, not sure that this instruction accepts an S prefix. We don't apply it in the
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// interpreter. But whatever.
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixD(dregs, sz, _VD);
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MIPSReg tempregs[4];
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for (int i = 0; i < n; ++i) {
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if (!IsOverlapSafe(dregs[i], i, n, sregs)) {
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tempregs[i] = fpr.GetTempV();
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} else {
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tempregs[i] = dregs[i];
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}
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}
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fp.MOVI2F(S0, 1.0f, SCRATCH1);
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for (int i = 0; i < n; ++i) {
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fpr.MapDirtyInV(tempregs[i], sregs[i]);
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// Let's do it integer registers for now. NEON later.
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// There's gotta be a shorter way, can't find one though that takes
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// care of NaNs like the interpreter (ignores them and just operates on the bits).
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fp.FSUB(fpr.V(tempregs[i]), S0, fpr.V(sregs[i]));
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}
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for (int i = 0; i < n; ++i) {
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if (dregs[i] != tempregs[i]) {
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fpr.MapDirtyInV(dregs[i], tempregs[i]);
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fp.FMOV(fpr.V(dregs[i]), fpr.V(tempregs[i]));
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}
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}
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ApplyPrefixD(dregs, sz);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_ColorConv(MIPSOpcode op) {
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DISABLE;
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}
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