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Unify JitOptions across the backends.

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This is required to make ExtractIR not a member of the various backends.
This commit is contained in:
Henrik Rydgård 2015-04-12 11:41:26 -07:00 committed by Unknown W. Brackets
parent 7bf67509d1
commit d014d420db
19 changed files with 102 additions and 102 deletions
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2
CMakeLists.txt
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@ -1342,6 +1342,8 @@ add_library(${CoreLibName} ${CoreLinkType}
Core/MIPS/JitCommon/NativeJit.h
Core/MIPS/JitCommon/JitBlockCache.cpp
Core/MIPS/JitCommon/JitBlockCache.h
Core/MIPS/JitCommon/JitState.cpp
Core/MIPS/JitCommon/JitState.h
Core/MIPS/MIPS.cpp
Core/MIPS/MIPS.h
Core/MIPS/MIPSAnalyst.cpp

3
Core/Core.vcxproj
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@ -415,6 +415,7 @@
</ClCompile>
<ClCompile Include="MIPS\JitCommon\JitBlockCache.cpp" />
<ClCompile Include="MIPS\JitCommon\JitCommon.cpp" />
<ClCompile Include="MIPS\JitCommon\JitState.cpp" />
<ClCompile Include="Mips\MIPS.cpp" />
<ClCompile Include="Mips\MIPSAnalyst.cpp" />
<ClCompile Include="MIPS\MIPSAsm.cpp" />
@ -718,4 +719,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
</Project>
</Project>

5
Core/Core.vcxproj.filters
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@ -593,6 +593,9 @@
<ClCompile Include="Util\DisArm64.cpp">
<Filter>Util</Filter>
</ClCompile>
<ClCompile Include="MIPS\JitCommon\JitState.cpp">
<Filter>MIPS\JitCommon</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="ELF\ElfReader.h">
@ -1122,4 +1125,4 @@
<None Include="..\android\jni\Android.mk" />
<None Include="GameLogNotes.txt" />
</ItemGroup>
</Project>
</Project>

32
Core/MIPS/ARM/ArmJit.h
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@ -34,36 +34,6 @@
namespace MIPSComp
{
struct ArmJitOptions
{
ArmJitOptions() {
enableBlocklink = true;
downcountInRegister = true;
useBackJump = false;
useForwardJump = false;
cachePointers = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
useNEONVFPU = false; // true
if (!cpu_info.bNEON)
useNEONVFPU = false;
}
bool useNEONVFPU;
bool enableBlocklink;
bool downcountInRegister;
bool useBackJump;
bool useForwardJump;
bool cachePointers;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
class ArmJit : public ArmGen::ARMXCodeBlock
{
public:
@ -305,7 +275,7 @@ private:
void Comp_ITypeMemLR(MIPSOpcode op, bool load);
JitBlockCache blocks;
ArmJitOptions jo;
JitOptions jo;
JitState js;
ArmRegCache gpr;

2
Core/MIPS/ARM/ArmRegCache.cpp
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@ -29,7 +29,7 @@
using namespace ArmGen;
using namespace ArmJitConstants;
ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void ArmRegCache::Init(ARMXEmitter *emitter) {

6
Core/MIPS/ARM/ArmRegCache.h
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@ -82,13 +82,13 @@ struct RegMIPS {
};
namespace MIPSComp {
struct ArmJitOptions;
struct JitOptions;
struct JitState;
}
class ArmRegCache {
public:
ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~ArmRegCache() {}
void Init(ArmGen::ARMXEmitter *emitter);
@ -143,7 +143,7 @@ private:
MIPSState *mips_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::ArmJitOptions *jo_;
MIPSComp::JitOptions *jo_;
u32 compilerPC_;
enum {

2
Core/MIPS/ARM/ArmRegCacheFPU.cpp
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@ -27,7 +27,7 @@
using namespace ArmGen;
using namespace ArmJitConstants;
ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
if (cpu_info.bNEON) {
numARMFpuReg_ = 32;
} else {

6
Core/MIPS/ARM/ArmRegCacheFPU.h
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@ -77,13 +77,13 @@ struct FPURegMIPS {
};
namespace MIPSComp {
struct ArmJitOptions;
struct JitOptions;
struct JitState;
}
class ArmRegCacheFPU {
public:
ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~ArmRegCacheFPU() {}
void Init(ArmGen::ARMXEmitter *emitter);
@ -191,7 +191,7 @@ private:
MIPSState *mips_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::ArmJitOptions *jo_;
MIPSComp::JitOptions *jo_;
int numARMFpuReg_;
int qTime_;

28
Core/MIPS/ARM64/Arm64Jit.h
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@ -34,32 +34,6 @@
namespace MIPSComp
{
struct Arm64JitOptions
{
Arm64JitOptions() {
enableBlocklink = true;
useBackJump = false;
useForwardJump = false;
cachePointers = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
useASIMDVFPU = false; // true
}
bool useASIMDVFPU;
bool enableBlocklink;
bool useBackJump;
bool useForwardJump;
bool cachePointers;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
class Arm64Jit : public Arm64Gen::ARM64CodeBlock
{
public:
@ -263,7 +237,7 @@ private:
void Comp_ITypeMemLR(MIPSOpcode op, bool load);
JitBlockCache blocks;
Arm64JitOptions jo;
JitOptions jo;
JitState js;
Arm64RegCache gpr;

2
Core/MIPS/ARM64/Arm64RegCache.cpp
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@ -29,7 +29,7 @@
using namespace Arm64Gen;
using namespace Arm64JitConstants;
Arm64RegCache::Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
Arm64RegCache::Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void Arm64RegCache::Init(ARM64XEmitter *emitter) {

6
Core/MIPS/ARM64/Arm64RegCache.h
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@ -85,13 +85,13 @@ struct RegMIPS {
};
namespace MIPSComp {
struct Arm64JitOptions;
struct JitOptions;
struct JitState;
}
class Arm64RegCache {
public:
Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo);
Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~Arm64RegCache() {}
void Init(Arm64Gen::ARM64XEmitter *emitter);
@ -146,7 +146,7 @@ private:
MIPSState *mips_;
Arm64Gen::ARM64XEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::Arm64JitOptions *jo_;
MIPSComp::JitOptions *jo_;
u32 compilerPC_;
enum {

2
Core/MIPS/ARM64/Arm64RegCacheFPU.cpp
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@ -27,7 +27,7 @@
using namespace Arm64Gen;
using namespace Arm64JitConstants;
Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
numARMFpuReg_ = 32;
}

6
Core/MIPS/ARM64/Arm64RegCacheFPU.h
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@ -77,13 +77,13 @@ struct FPURegMIPS {
};
namespace MIPSComp {
struct Arm64JitOptions;
struct JitOptions;
struct JitState;
}
class Arm64RegCacheFPU {
public:
Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo);
Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~Arm64RegCacheFPU() {}
void Init(Arm64Gen::ARM64XEmitter *emitter, Arm64Gen::ARM64FloatEmitter *fp);
@ -159,7 +159,7 @@ private:
Arm64Gen::ARM64XEmitter *emit_;
Arm64Gen::ARM64FloatEmitter *fp_;
MIPSComp::JitState *js_;
MIPSComp::Arm64JitOptions *jo_;
MIPSComp::JitOptions *jo_;
int numARMFpuReg_;
int qTime_;

49
Core/MIPS/JitCommon/JitState.cpp Normal file
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@ -0,0 +1,49 @@
// Copyright (c) 2013- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Common/CPUDetect.h"
#include "Core/MIPS/JitCommon/JitState.h"
namespace MIPSComp {
JitOptions::JitOptions() {
// x86
enableVFPUSIMD = true;
// Set by Asm if needed.
reserveR15ForAsm = false;
// ARM/ARM64
useBackJump = false;
useForwardJump = false;
cachePointers = true;
// ARM only
downcountInRegister = true;
useNEONVFPU = false; // true
if (!cpu_info.bNEON)
useNEONVFPU = false;
//ARM64
useASIMDVFPU = false; // true
// Common
enableBlocklink = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
}
}

25
Core/MIPS/JitCommon/JitState.h
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@ -175,4 +175,29 @@ namespace MIPSComp {
}
}
};
struct JitOptions {
JitOptions();
// x86
bool enableVFPUSIMD;
bool reserveR15ForAsm;
// ARM/ARM64
bool useBackJump;
bool useForwardJump;
bool cachePointers;
// ARM only
bool useNEONVFPU;
bool downcountInRegister;
// ARM64 only
bool useASIMDVFPU;
// Common
bool enableBlocklink;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
}

12
Core/MIPS/x86/Jit.cpp
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@ -114,18 +114,6 @@ static void JitLogMiss(MIPSOpcode op)
func(op);
}
JitOptions::JitOptions()
{
enableBlocklink = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
enableVFPUSIMD = true;
// Set by Asm if needed.
reserveR15ForAsm = false;
}
#ifdef _MSC_VER
// JitBlockCache doesn't use this, just stores it.
#pragma warning(disable:4355)

13
Core/MIPS/x86/Jit.h
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@ -41,19 +41,6 @@ namespace MIPSComp
// This is called when Jit hits a breakpoint. Returns 1 when hit.
u32 JitBreakpoint();
struct JitOptions
{
JitOptions();
bool enableBlocklink;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
bool enableVFPUSIMD;
bool reserveR15ForAsm;
};
// TODO: Hmm, humongous.
struct RegCacheState {
GPRRegCacheState gpr;

1
android/jni/Android.mk
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@ -314,6 +314,7 @@ EXEC_AND_LIB_FILES := \
$(SRC)/Core/FileSystems/tlzrc.cpp \
$(SRC)/Core/MIPS/JitCommon/JitCommon.cpp \
$(SRC)/Core/MIPS/JitCommon/JitBlockCache.cpp \
$(SRC)/Core/MIPS/JitCommon/JitState.cpp \
$(SRC)/Core/Util/AudioFormat.cpp \
$(SRC)/Core/Util/GameManager.cpp \
$(SRC)/Core/Util/BlockAllocator.cpp \

2
unittest/TestArmEmitter.cpp
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@ -199,7 +199,7 @@ bool TestArmEmitter() {
MIPSState mips;
MIPSComp::JitState js;
MIPSComp::ArmJitOptions jo;
MIPSComp::JitOptions jo;
ArmRegCacheFPU fpr(&mips, &js, &jo);
fpr.SetEmitter(&emitter);
int C000 = GetColumnName(0, M_4x4, 0, 0);