From d021706eb3f242dcd0b4c8df5fc37c889e4dbbe9 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Thu, 24 Aug 2023 23:09:41 -0700
Subject: [PATCH] x86jit: Implement conditional assigns.

---
 Core/MIPS/x86/X64IRCompALU.cpp | 45 +++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/x86/X64IRCompALU.cpp b/Core/MIPS/x86/X64IRCompALU.cpp
index 39282a9f7a..4f45f6cd46 100644
--- a/Core/MIPS/x86/X64IRCompALU.cpp
+++ b/Core/MIPS/x86/X64IRCompALU.cpp
@@ -233,10 +233,53 @@ void X64JitBackend::CompIR_CondAssign(IRInst inst) {
 
 	switch (inst.op) {
 	case IROp::MovZ:
+		if (inst.dest != inst.src2) {
+			regs_.Map(inst);
+			CMP(32, regs_.R(inst.src1), Imm32(0));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_Z);
+		}
+		break;
+
 	case IROp::MovNZ:
+		if (inst.dest != inst.src2) {
+			regs_.Map(inst);
+			CMP(32, regs_.R(inst.src1), Imm32(0));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_NZ);
+		}
+		break;
+
 	case IROp::Max:
+		regs_.Map(inst);
+		if (inst.src1 == inst.src2) {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else if (inst.dest == inst.src1) {
+			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_L);
+		} else if (inst.dest == inst.src2) {
+			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src1), CC_G);
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			CMP(32, regs_.R(inst.dest), regs_.R(inst.src2));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_L);
+		}
+		break;
+
 	case IROp::Min:
-		CompIR_Generic(inst);
+		regs_.Map(inst);
+		if (inst.src1 == inst.src2) {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else if (inst.dest == inst.src1) {
+			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_G);
+		} else if (inst.dest == inst.src2) {
+			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src1), CC_L);
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			CMP(32, regs_.R(inst.dest), regs_.R(inst.src2));
+			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_G);
+		}
 		break;
 
 	default: