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32-bit fixes

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This commit is contained in:
Henrik Rydgård 2017-07-07 13:57:37 +02:00
parent e5a7d0df95
commit d312086a61
1 changed files with 4 additions and 4 deletions
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8
Core/MIPS/x86/CompVFPU.cpp
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@ -2352,12 +2352,12 @@ void Jit::Comp_VV2Op(MIPSOpcode op) {
DIVSS(tempxregs[i], R(XMM0));
break;
case 18: // d[i] = sinf((float)M_PI_2 * s[i]); break; //vsin
LEA(64, RDX, MIPSSTATE_VAR(sincostemp));
LEA(PTRBITS, RDX, MIPSSTATE_VAR(sincostemp[0]));
trigCallHelper(&SinOnly, sregs[i]);
MOVSS(tempxregs[i], MIPSSTATE_VAR(sincostemp[0]));
break;
case 19: // d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos
LEA(64, RDX, MIPSSTATE_VAR(sincostemp));
LEA(PTRBITS, RDX, MIPSSTATE_VAR(sincostemp[0]));
trigCallHelper(&CosOnly, sregs[i]);
MOVSS(tempxregs[i], MIPSSTATE_VAR(sincostemp[1]));
break;
@ -2373,7 +2373,7 @@ void Jit::Comp_VV2Op(MIPSOpcode op) {
ANDPS(tempxregs[i], MatR(TEMPREG));
break;
case 23: // d[i] = asinf(s[i]) / M_PI_2; break; //vasin
LEA(64, RDX, MIPSSTATE_VAR(sincostemp));
LEA(PTRBITS, RDX, MIPSSTATE_VAR(sincostemp[0]));
trigCallHelper(&ASinScaled, sregs[i]);
MOVSS(tempxregs[i], MIPSSTATE_VAR(sincostemp[0]));
break;
@ -2385,7 +2385,7 @@ void Jit::Comp_VV2Op(MIPSOpcode op) {
MOVSS(tempxregs[i], R(XMM0));
break;
case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin
LEA(64, RDX, MIPSSTATE_VAR(sincostemp));
LEA(PTRBITS, RDX, MIPSSTATE_VAR(sincostemp[0]));
trigCallHelper(&NegSinOnly, sregs[i]);
MOVSS(tempxregs[i], MIPSSTATE_VAR(sincostemp[0]));
break;