From e5467d270659ea3a251c91f4c5fed7b3d9ea068b Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Fri, 1 Dec 2023 22:40:08 -0800
Subject: [PATCH] riscv: Add czero instruction encoding.

---
 Common/RiscVEmitter.cpp | 21 +++++++++++++++++++++
 Common/RiscVEmitter.h   |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/Common/RiscVEmitter.cpp b/Common/RiscVEmitter.cpp
index eae13d18b2..936ee4da77 100644
--- a/Common/RiscVEmitter.cpp
+++ b/Common/RiscVEmitter.cpp
@@ -78,6 +78,11 @@ static inline bool SupportsBitmanip(char zbx) {
 	}
 }
 
+static inline bool SupportsIntConditional() {
+	// TODO: cpu_info.RiscV_Zicond;
+	return false;
+}
+
 static inline bool SupportsFloatHalf(bool allowMin = false) {
 	// TODO
 	return false;
@@ -219,6 +224,9 @@ enum class Funct3 {
 	BSET = 0b001,
 	BEXT = 0b101,
 
+	CZERO_EQZ = 0b101,
+	CZERO_NEZ = 0b111,
+
 	C_ADDI4SPN = 0b000,
 	C_FLD = 0b001,
 	C_LW = 0b010,
@@ -282,6 +290,7 @@ enum class Funct7 {
 
 	ADDUW_ZEXT = 0b0000100,
 	MINMAX_CLMUL = 0b0000101,
+	CZERO = 0b0000111,
 	SH_ADD = 0b0010000,
 	BSET_ORC = 0b0010100,
 	NOT = 0b0100000,
@@ -4301,6 +4310,18 @@ void RiscVEmitter::BSETI(RiscVReg rd, RiscVReg rs1, u32 shamt) {
 	Write32(EncodeGIShift(Opcode32::OP_IMM, rd, Funct3::BSET, rs1, shamt, Funct7::BSET_ORC));
 }
 
+void RiscVEmitter::CZERO_EQZ(RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
+	_assert_msg_(rd != R_ZERO, "%s should avoid write to zero", __func__);
+	_assert_msg_(SupportsIntConditional(), "%s instruction unsupported without Zicond", __func__);
+	Write32(EncodeR(Opcode32::OP, rd, Funct3::CZERO_EQZ, rs1, rs2, Funct7::CZERO));
+}
+
+void RiscVEmitter::CZERO_NEZ(RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
+	_assert_msg_(rd != R_ZERO, "%s should avoid write to zero", __func__);
+	_assert_msg_(SupportsIntConditional(), "%s instruction unsupported without Zicond", __func__);
+	Write32(EncodeR(Opcode32::OP, rd, Funct3::CZERO_NEZ, rs1, rs2, Funct7::CZERO));
+}
+
 bool RiscVEmitter::AutoCompress() const {
 	return SupportsCompressed() && autoCompress_;
 }
diff --git a/Common/RiscVEmitter.h b/Common/RiscVEmitter.h
index 3923b50d44..20a98f44f8 100644
--- a/Common/RiscVEmitter.h
+++ b/Common/RiscVEmitter.h
@@ -965,6 +965,9 @@ public:
 	void BSET(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
 	void BSETI(RiscVReg rd, RiscVReg rs1, u32 shamt);
 
+	void CZERO_EQZ(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
+	void CZERO_NEZ(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
+
 	// Compressed instructions.
 	void C_ADDI4SPN(RiscVReg rd, u32 nzuimm10);
 	void C_FLD(RiscVReg rd, RiscVReg addr, u8 uimm8);