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Avoid reseved identifiers like _SP, etc.

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R_SP is not that bad.
This commit is contained in:
Unknown W. Brackets 2013-12-29 14:25:34 -08:00
parent 5dbc26aec8
commit e6b2d00a2f
5 changed files with 28 additions and 32 deletions
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2
Common/ArmEmitter.cpp
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@ -395,7 +395,7 @@ void ARMXEmitter::MOVI2R(ARMReg reg, u32 val, bool optimize)
// Use literal pool for ARMv6.
// Disabled for now as it is crashing since Vertex Decoder JIT
// AddNewLit(val);
// LDR(reg, _PC); // To be backpatched later
// LDR(reg, R_PC); // To be backpatched later
}
#endif
}

42
Common/ArmEmitter.h
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@ -27,11 +27,7 @@
#endif
#include <vector>
#undef _IP
#undef R0
#undef _SP
#undef _LR
#undef _PC
// VCVT flags
#define TO_FLOAT 0
@ -51,7 +47,7 @@ enum ARMReg
// R13 - R15 are SP, LR, and PC.
// Almost always referred to by name instead of register number
R12 = 12, R13 = 13, R14 = 14, R15 = 15,
_IP = 12, _SP = 13, _LR = 14, _PC = 15,
R_IP = 12, R_SP = 13, R_LR = 14, R_PC = 15,
// VFP single precision registers
@ -738,41 +734,41 @@ public:
// Notes:
// Rm == _PC is interpreted as no offset, otherwise, effective address is sum of Rn and Rm
// Rm == R_PC is interpreted as no offset, otherwise, effective address is sum of Rn and Rm
// Rm == R13 is interpreted as VLD1, .... [Rn]! Added a REG_UPDATE pseudo register.
// Load/store multiple registers full of elements (a register is a D register)
// Specifying alignment when it can be guaranteed is documented to improve load/store performance.
// For example, when loading a set of four 64-bit registers that we know is 32-byte aligned, we should specify ALIGN_256.
void VLD1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VST1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VLD1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VST1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
// Load/store single lanes of D registers
void VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm = _PC);
void VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm = _PC);
void VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm = R_PC);
void VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm = R_PC);
// Load one value into all lanes of a D or a Q register (either supported, all formats should work).
void VLD1_all_lanes(u32 Size, ARMReg Vd, ARMReg Rn, bool aligned, ARMReg Rm = _PC);
void VLD1_all_lanes(u32 Size, ARMReg Vd, ARMReg Rn, bool aligned, ARMReg Rm = R_PC);
/*
// Deinterleave two loads... or something. TODO
void VLD2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VST2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VLD2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VST2(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VLD2_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
void VST2_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
void VLD2_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = R_PC);
void VST2_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = R_PC);
void VLD3(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VST3(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VLD3(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VST3(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VLD3_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
void VST3_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
void VLD3_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = R_PC);
void VST3_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = R_PC);
void VLD4(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VST4(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
void VLD4(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VST4(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align = ALIGN_NONE, ARMReg Rm = R_PC);
void VLD4_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
void VST4_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = _PC);
void VLD4_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = R_PC);
void VST4_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, ARMReg Rm = R_PC);
*/
void VMRS_APSR();

8
Core/MIPS/ARM/ArmAsm.cpp
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@ -83,12 +83,12 @@ void Jit::GenerateFixedCode()
SetCC(CC_AL);
PUSH(9, R4, R5, R6, R7, R8, R9, R10, R11, _LR);
PUSH(9, R4, R5, R6, R7, R8, R9, R10, R11, R_LR);
// Take care to 8-byte align stack for function calls.
// We are misaligned here because of an odd number of args for PUSH.
// It's not like x86 where you need to account for an extra 4 bytes
// consumed by CALL.
SUB(_SP, _SP, 4);
SUB(R_SP, R_SP, 4);
// Now we are correctly aligned and plan to stay that way.
// TODO: R12 should be usable for regalloc but will get thrashed by C code.
@ -185,9 +185,9 @@ void Jit::GenerateFixedCode()
breakpointBailout = GetCodePtr();
SaveDowncount();
ADD(_SP, _SP, 4);
ADD(R_SP, R_SP, 4);
POP(9, R4, R5, R6, R7, R8, R9, R10, R11, _PC); // Returns
POP(9, R4, R5, R6, R7, R8, R9, R10, R11, R_PC); // Returns
// Uncomment if you want to see the output...

4
GPU/GLES/VertexDecoderArm.cpp
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@ -156,7 +156,7 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec) {
SetCC(CC_AL);
PUSH(6, R4, R5, R6, R7, R8, _LR);
PUSH(6, R4, R5, R6, R7, R8, R_LR);
// Keep the scale/offset in a few fp registers if we need it.
// This step can be NEON-ized but the savings would be miniscule.
@ -247,7 +247,7 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec) {
SUBS(counterReg, counterReg, 1);
B_CC(CC_NEQ, loopStart);
POP(6, R4, R5, R6, R7, R8, _PC);
POP(6, R4, R5, R6, R7, R8, R_PC);
FlushLitPool();
FlushIcache();

4
android/jni/ArmEmitterTest.cpp
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@ -35,7 +35,7 @@ void TestCode::Generate()
{
testCodePtr = this->GetCodePtr();
// Sonic1 commented that R11 is the frame pointer in debug mode, whatever "debug mode" means.
PUSH(2, R11, _LR);
PUSH(2, R11, R_LR);
// Load the three pointers
/*
@ -88,7 +88,7 @@ void TestCode::Generate()
VSTR(S12, R11, 4 * (32 + 31));
*/
//VSTR(S2, R0, 8);
POP(2, R11, _PC); // Yup, this is how you return.
POP(2, R11, R_PC); // Yup, this is how you return.
FlushLitPool();
FlushIcache();