From e75e7a0e43119c587ab10182f29269799f17695b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Fri, 24 May 2024 23:08:28 +0200
Subject: [PATCH] Add an optimizeForInterpreter flag

---
 Core/MIPS/ARM64/Arm64IRJit.cpp | 1 +
 Core/MIPS/IR/IRFrontend.cpp    | 9 +++++++--
 Core/MIPS/IR/IRInst.h          | 1 +
 Core/MIPS/IR/IRJit.cpp         | 3 +++
 Core/MIPS/JitCommon/JitState.h | 4 ++--
 Core/MIPS/RiscV/RiscVJit.cpp   | 1 +
 Core/MIPS/x86/X64IRJit.cpp     | 1 +
 7 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/Core/MIPS/ARM64/Arm64IRJit.cpp b/Core/MIPS/ARM64/Arm64IRJit.cpp
index 10438af30b..26d9913bdc 100644
--- a/Core/MIPS/ARM64/Arm64IRJit.cpp
+++ b/Core/MIPS/ARM64/Arm64IRJit.cpp
@@ -44,6 +44,7 @@ Arm64JitBackend::Arm64JitBackend(JitOptions &jitopt, IRBlockCache &blocks)
 	if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
 		jo.enablePointerify = false;
 	}
+	jo.optimizeForInterpreter = false;
 #ifdef MASKED_PSP_MEMORY
 	jo.enablePointerify = false;
 #endif
diff --git a/Core/MIPS/IR/IRFrontend.cpp b/Core/MIPS/IR/IRFrontend.cpp
index 2270484391..36efd6ad72 100644
--- a/Core/MIPS/IR/IRFrontend.cpp
+++ b/Core/MIPS/IR/IRFrontend.cpp
@@ -277,7 +277,7 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
 	IRWriter simplified;
 	IRWriter *code = &ir;
 	if (!js.hadBreakpoints) {
-		static const IRPassFunc passes[] = {
+		std::vector<IRPassFunc> passes{
 			&ApplyMemoryValidation,
 			&RemoveLoadStoreLeftRight,
 			&OptimizeFPMoves,
@@ -288,7 +288,12 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
 			// &MergeLoadStore,
 			// &ThreeOpToTwoOp,
 		};
-		if (IRApplyPasses(passes, ARRAY_SIZE(passes), ir, simplified, opts))
+
+		if (opts.optimizeForInterpreter) {
+			// Add special passes here.
+			// passes.push_back(&ReorderLoadStore);
+		}
+		if (IRApplyPasses(passes.data(), passes.size(), ir, simplified, opts))
 			logBlocks = 1;
 		code = &simplified;
 		//if (ir.GetInstructions().size() >= 24)
diff --git a/Core/MIPS/IR/IRInst.h b/Core/MIPS/IR/IRInst.h
index cec31c7ee3..e2d855a3e0 100644
--- a/Core/MIPS/IR/IRInst.h
+++ b/Core/MIPS/IR/IRInst.h
@@ -405,6 +405,7 @@ struct IROptions {
 	bool unalignedLoadStoreVec4;
 	bool preferVec4;
 	bool preferVec4Dot;
+	bool optimizeForInterpreter;
 };
 
 const IRMeta *GetIRMeta(IROp op);
diff --git a/Core/MIPS/IR/IRJit.cpp b/Core/MIPS/IR/IRJit.cpp
index c89c5fa41f..f3ce1c008b 100644
--- a/Core/MIPS/IR/IRJit.cpp
+++ b/Core/MIPS/IR/IRJit.cpp
@@ -48,6 +48,8 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
 	// blTrampolines_ = kernelMemory.Alloc(size, true, "trampoline");
 	InitIR();
 
+	jo.optimizeForInterpreter = true;
+
 	IROptions opts{};
 	opts.disableFlags = g_Config.uJitDisableFlags;
 #if PPSSPP_ARCH(RISCV64)
@@ -65,6 +67,7 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
 	opts.unalignedLoadStoreVec4 = false;
 	opts.preferVec4 = true;
 #endif
+	opts.optimizeForInterpreter = jo.optimizeForInterpreter;
 	frontend_.SetOptions(opts);
 }
 
diff --git a/Core/MIPS/JitCommon/JitState.h b/Core/MIPS/JitCommon/JitState.h
index 37acde3b62..6f5b9f2628 100644
--- a/Core/MIPS/JitCommon/JitState.h
+++ b/Core/MIPS/JitCommon/JitState.h
@@ -237,6 +237,8 @@ namespace MIPSComp {
 		// ARM64 and RV64
 		bool useStaticAlloc;
 		bool enablePointerify;
+		// IR Interpreter
+		bool optimizeForInterpreter;
 
 		// Common
 		bool enableBlocklink;
@@ -245,6 +247,4 @@ namespace MIPSComp {
 		bool continueJumps;
 		int continueMaxInstructions;
 	};
-
 }
-
diff --git a/Core/MIPS/RiscV/RiscVJit.cpp b/Core/MIPS/RiscV/RiscVJit.cpp
index 60d5c5f929..65ebffc7b9 100644
--- a/Core/MIPS/RiscV/RiscVJit.cpp
+++ b/Core/MIPS/RiscV/RiscVJit.cpp
@@ -39,6 +39,7 @@ RiscVJitBackend::RiscVJitBackend(JitOptions &jitopt, IRBlockCache &blocks)
 	if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
 		jo.enablePointerify = false;
 	}
+	jo.optimizeForInterpreter = false;
 
 	// Since we store the offset, this is as big as it can be.
 	// We could shift off one bit to double it, would need to change RiscVAsm.
diff --git a/Core/MIPS/x86/X64IRJit.cpp b/Core/MIPS/x86/X64IRJit.cpp
index dbcddee3f5..be6a374697 100644
--- a/Core/MIPS/x86/X64IRJit.cpp
+++ b/Core/MIPS/x86/X64IRJit.cpp
@@ -41,6 +41,7 @@ X64JitBackend::X64JitBackend(JitOptions &jitopt, IRBlockCache &blocks)
 	if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
 		jo.enablePointerify = false;
 	}
+	jo.optimizeForInterpreter = false;
 
 	// Since we store the offset, this is as big as it can be.
 	AllocCodeSpace(1024 * 1024 * 16);