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Add an optimizeForInterpreter flag
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parent
9d11c35dd8
commit
e75e7a0e43
@ -44,6 +44,7 @@ Arm64JitBackend::Arm64JitBackend(JitOptions &jitopt, IRBlockCache &blocks)
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if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
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jo.enablePointerify = false;
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}
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jo.optimizeForInterpreter = false;
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#ifdef MASKED_PSP_MEMORY
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jo.enablePointerify = false;
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#endif
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@ -277,7 +277,7 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
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IRWriter simplified;
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IRWriter *code = &ir;
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if (!js.hadBreakpoints) {
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static const IRPassFunc passes[] = {
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std::vector<IRPassFunc> passes{
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&ApplyMemoryValidation,
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&RemoveLoadStoreLeftRight,
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&OptimizeFPMoves,
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@ -288,7 +288,12 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
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// &MergeLoadStore,
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// &ThreeOpToTwoOp,
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};
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if (IRApplyPasses(passes, ARRAY_SIZE(passes), ir, simplified, opts))
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if (opts.optimizeForInterpreter) {
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// Add special passes here.
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// passes.push_back(&ReorderLoadStore);
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}
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if (IRApplyPasses(passes.data(), passes.size(), ir, simplified, opts))
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logBlocks = 1;
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code = &simplified;
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//if (ir.GetInstructions().size() >= 24)
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@ -405,6 +405,7 @@ struct IROptions {
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bool unalignedLoadStoreVec4;
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bool preferVec4;
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bool preferVec4Dot;
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bool optimizeForInterpreter;
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};
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const IRMeta *GetIRMeta(IROp op);
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@ -48,6 +48,8 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
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// blTrampolines_ = kernelMemory.Alloc(size, true, "trampoline");
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InitIR();
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jo.optimizeForInterpreter = true;
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IROptions opts{};
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opts.disableFlags = g_Config.uJitDisableFlags;
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#if PPSSPP_ARCH(RISCV64)
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@ -65,6 +67,7 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
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opts.unalignedLoadStoreVec4 = false;
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opts.preferVec4 = true;
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#endif
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opts.optimizeForInterpreter = jo.optimizeForInterpreter;
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frontend_.SetOptions(opts);
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}
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@ -237,6 +237,8 @@ namespace MIPSComp {
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// ARM64 and RV64
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bool useStaticAlloc;
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bool enablePointerify;
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// IR Interpreter
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bool optimizeForInterpreter;
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// Common
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bool enableBlocklink;
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@ -245,6 +247,4 @@ namespace MIPSComp {
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bool continueJumps;
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int continueMaxInstructions;
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};
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}
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@ -39,6 +39,7 @@ RiscVJitBackend::RiscVJitBackend(JitOptions &jitopt, IRBlockCache &blocks)
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if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
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jo.enablePointerify = false;
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}
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jo.optimizeForInterpreter = false;
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// Since we store the offset, this is as big as it can be.
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// We could shift off one bit to double it, would need to change RiscVAsm.
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@ -41,6 +41,7 @@ X64JitBackend::X64JitBackend(JitOptions &jitopt, IRBlockCache &blocks)
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if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
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jo.enablePointerify = false;
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}
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jo.optimizeForInterpreter = false;
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// Since we store the offset, this is as big as it can be.
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AllocCodeSpace(1024 * 1024 * 16);
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