Add an optimizeForInterpreter flag

This commit is contained in:
Henrik Rydgård 2024-05-24 23:08:28 +02:00
parent 9d11c35dd8
commit e75e7a0e43
7 changed files with 16 additions and 4 deletions

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@ -44,6 +44,7 @@ Arm64JitBackend::Arm64JitBackend(JitOptions &jitopt, IRBlockCache &blocks)
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
jo.enablePointerify = false;
}
jo.optimizeForInterpreter = false;
#ifdef MASKED_PSP_MEMORY
jo.enablePointerify = false;
#endif

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@ -277,7 +277,7 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
IRWriter simplified;
IRWriter *code = &ir;
if (!js.hadBreakpoints) {
static const IRPassFunc passes[] = {
std::vector<IRPassFunc> passes{
&ApplyMemoryValidation,
&RemoveLoadStoreLeftRight,
&OptimizeFPMoves,
@ -288,7 +288,12 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, u32 &m
// &MergeLoadStore,
// &ThreeOpToTwoOp,
};
if (IRApplyPasses(passes, ARRAY_SIZE(passes), ir, simplified, opts))
if (opts.optimizeForInterpreter) {
// Add special passes here.
// passes.push_back(&ReorderLoadStore);
}
if (IRApplyPasses(passes.data(), passes.size(), ir, simplified, opts))
logBlocks = 1;
code = &simplified;
//if (ir.GetInstructions().size() >= 24)

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@ -405,6 +405,7 @@ struct IROptions {
bool unalignedLoadStoreVec4;
bool preferVec4;
bool preferVec4Dot;
bool optimizeForInterpreter;
};
const IRMeta *GetIRMeta(IROp op);

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@ -48,6 +48,8 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
// blTrampolines_ = kernelMemory.Alloc(size, true, "trampoline");
InitIR();
jo.optimizeForInterpreter = true;
IROptions opts{};
opts.disableFlags = g_Config.uJitDisableFlags;
#if PPSSPP_ARCH(RISCV64)
@ -65,6 +67,7 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
opts.unalignedLoadStoreVec4 = false;
opts.preferVec4 = true;
#endif
opts.optimizeForInterpreter = jo.optimizeForInterpreter;
frontend_.SetOptions(opts);
}

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@ -237,6 +237,8 @@ namespace MIPSComp {
// ARM64 and RV64
bool useStaticAlloc;
bool enablePointerify;
// IR Interpreter
bool optimizeForInterpreter;
// Common
bool enableBlocklink;
@ -245,6 +247,4 @@ namespace MIPSComp {
bool continueJumps;
int continueMaxInstructions;
};
}

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@ -39,6 +39,7 @@ RiscVJitBackend::RiscVJitBackend(JitOptions &jitopt, IRBlockCache &blocks)
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
jo.enablePointerify = false;
}
jo.optimizeForInterpreter = false;
// Since we store the offset, this is as big as it can be.
// We could shift off one bit to double it, would need to change RiscVAsm.

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@ -41,6 +41,7 @@ X64JitBackend::X64JitBackend(JitOptions &jitopt, IRBlockCache &blocks)
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
jo.enablePointerify = false;
}
jo.optimizeForInterpreter = false;
// Since we store the offset, this is as big as it can be.
AllocCodeSpace(1024 * 1024 * 16);