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riscv: Centralize reg allocation.
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parent
b30daa5760
commit
ebab0e1591
@ -21,6 +21,8 @@
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#include <cstring>
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#include "Common/Log.h"
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#include "Common/LogReporting.h"
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#include "Core/MIPS/IR/IRAnalysis.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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#include "Core/MIPS/IR/IRInst.h"
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#include "Core/MIPS/IR/IRJit.h"
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@ -90,10 +92,10 @@ void IRImmRegCache::MapDirtyInIn(IRReg rd, IRReg rs, IRReg rt) {
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Flush(rt);
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}
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IRNativeRegCache::IRNativeRegCache(MIPSComp::JitOptions *jo)
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IRNativeRegCacheBase::IRNativeRegCacheBase(MIPSComp::JitOptions *jo)
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: jo_(jo) {}
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void IRNativeRegCache::Start(MIPSComp::IRBlock *irBlock) {
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void IRNativeRegCacheBase::Start(MIPSComp::IRBlock *irBlock) {
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if (!initialReady_) {
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SetupInitialRegs();
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initialReady_ = true;
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@ -109,7 +111,7 @@ void IRNativeRegCache::Start(MIPSComp::IRBlock *irBlock) {
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nr[statics[i].nr].mipsReg = statics[i].mr;
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nr[statics[i].nr].pointerified = statics[i].pointerified && jo_->enablePointerify;
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nr[statics[i].nr].normalized32 = statics[i].normalized32;
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mr[statics[i].mr].loc = MIPSLoc::REG;
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mr[statics[i].mr].loc = statics[i].loc;
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mr[statics[i].mr].nReg = statics[i].nr;
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mr[statics[i].mr].isStatic = true;
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// Lock it until the very end.
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@ -120,10 +122,242 @@ void IRNativeRegCache::Start(MIPSComp::IRBlock *irBlock) {
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irIndex_ = 0;
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}
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void IRNativeRegCache::SetupInitialRegs() {
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void IRNativeRegCacheBase::SetupInitialRegs() {
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_assert_msg_(totalNativeRegs_ > 0, "totalNativeRegs_ was never set by backend");
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// Everything else is initialized in the struct.
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mrInitial_[MIPS_REG_ZERO].loc = MIPSLoc::IMM;
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mrInitial_[MIPS_REG_ZERO].imm = 0;
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}
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IRNativeReg IRNativeRegCacheBase::AllocateReg(MIPSLoc type) {
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_dbg_assert_(type == MIPSLoc::REG || type == MIPSLoc::FREG || type == MIPSLoc::VREG);
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IRNativeReg nreg = FindFreeReg(type);
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if (nreg != -1)
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return nreg;
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// Still nothing. Let's spill a reg and goto 10.
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bool clobbered;
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IRNativeReg bestToSpill = FindBestToSpill(type, true, &clobbered);
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if (bestToSpill == -1) {
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bestToSpill = FindBestToSpill(type, false, &clobbered);
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}
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if (bestToSpill != -1) {
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if (clobbered) {
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DiscardNativeReg(bestToSpill);
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} else {
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FlushNativeReg(bestToSpill);
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}
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// Now one must be free.
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return FindFreeReg(type);
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}
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// Uh oh, we have all of them spilllocked....
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ERROR_LOG_REPORT(JIT, "Out of spillable registers in block PC %08x, index %d", irBlock_->GetOriginalStart(), irIndex_);
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_assert_(bestToSpill != -1);
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return -1;
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}
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IRNativeReg IRNativeRegCacheBase::FindFreeReg(MIPSLoc type) const {
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int allocCount = 0, base = 0;
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const int *allocOrder = GetAllocationOrder(type, allocCount, base);
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for (int i = 0; i < allocCount; i++) {
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IRNativeReg nreg = IRNativeReg(allocOrder[i] - base);
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if (nr[nreg].mipsReg == IRREG_INVALID) {
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return nreg;
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}
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}
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return -1;
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}
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IRNativeReg IRNativeRegCacheBase::FindBestToSpill(MIPSLoc type, bool unusedOnly, bool *clobbered) const {
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int allocCount = 0, base = 0;
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const int *allocOrder = GetAllocationOrder(type, allocCount, base);
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static const int UNUSED_LOOKAHEAD_OPS = 30;
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IRSituation info;
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info.lookaheadCount = UNUSED_LOOKAHEAD_OPS;
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info.currentIndex = irIndex_;
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info.instructions = irBlock_->GetInstructions();
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info.numInstructions = irBlock_->GetNumInstructions();
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auto getUsage = [type, &info](IRReg mipsReg) {
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if (type == MIPSLoc::REG)
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return IRNextGPRUsage(mipsReg, info);
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else if (type == MIPSLoc::FREG || type == MIPSLoc::VREG)
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return IRNextFPRUsage(mipsReg - 32, info);
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_assert_msg_(false, "Unknown spill allocation type");
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return IRUsage::UNKNOWN;
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};
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*clobbered = false;
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for (int i = 0; i < allocCount; i++) {
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IRNativeReg nreg = IRNativeReg(allocOrder[i] - base);
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if (nr[nreg].mipsReg != IRREG_INVALID && mr[nr[nreg].mipsReg].spillLockIRIndex >= irIndex_)
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continue;
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if (nr[nreg].tempLockIRIndex >= irIndex_)
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continue;
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// As it's in alloc-order, we know it's not static so we don't need to check for that.
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IRReg mipsReg = nr[nreg].mipsReg;
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IRUsage usage = getUsage(mipsReg);
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// Awesome, a clobbered reg. Let's use it?
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if (usage == IRUsage::CLOBBERED) {
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// If multiple mips regs use this native reg (i.e. vector, HI/LO), check each.
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// Note: mipsReg points to the lowest numbered IRReg.
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bool canClobber = true;
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for (IRReg m = mipsReg + 1; mr[m].nReg == nreg && m < IRREG_INVALID && canClobber; ++m)
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canClobber = getUsage(mipsReg) == IRUsage::CLOBBERED;
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// Okay, if all can be clobbered, we're good to go.
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if (canClobber) {
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*clobbered = true;
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return nreg;
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}
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}
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// Not awesome. A used reg. Let's try to avoid spilling.
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if (!unusedOnly || usage == IRUsage::UNUSED) {
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// TODO: Use age or something to choose which register to spill?
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// TODO: Spill dirty regs first? or opposite?
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return nreg;
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}
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}
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return -1;
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}
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void IRNativeRegCacheBase::DiscardNativeReg(IRNativeReg nreg) {
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_assert_msg_(nreg >= 0 && nreg < totalNativeRegs_, "DiscardNativeReg on invalid register %d", nreg);
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if (nr[nreg].mipsReg != IRREG_INVALID) {
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_assert_(nr[nreg].mipsReg != MIPS_REG_ZERO);
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int8_t lanes = 0;
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for (IRReg m = nr[nreg].mipsReg; mr[m].nReg == nreg && m < IRREG_INVALID; ++m)
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lanes++;
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if (mr[nr[nreg].mipsReg].isStatic) {
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int numStatics;
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const StaticAllocation *statics = GetStaticAllocations(numStatics);
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// If it's not currently marked as in a reg, throw it away.
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for (IRReg m = nr[nreg].mipsReg; m < nr[nreg].mipsReg + lanes; ++m) {
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_assert_msg_(!mr[m].isStatic, "Reg in lane %d mismatched static status", m - nr[nreg].mipsReg);
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for (int i = 0; i < numStatics; i++) {
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if (m == statics[i].mr)
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mr[m].loc = statics[i].loc;
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}
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}
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} else {
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for (IRReg m = nr[nreg].mipsReg; m < nr[nreg].mipsReg + lanes; ++m) {
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mr[m].loc = MIPSLoc::MEM;
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mr[m].nReg = -1;
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mr[m].imm = 0;
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_assert_msg_(!mr[m].isStatic, "Reg in lane %d mismatched static status", m - nr[nreg].mipsReg);
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}
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nr[nreg].mipsReg = IRREG_INVALID;
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}
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}
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// Even for a static reg, we assume this means it's not pointerified anymore.
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nr[nreg].pointerified = false;
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nr[nreg].isDirty = false;
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nr[nreg].normalized32 = false;
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}
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void IRNativeRegCacheBase::FlushNativeReg(IRNativeReg nreg) {
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_assert_msg_(nreg >= 0 && nreg < totalNativeRegs_, "FlushNativeReg on invalid register %d", nreg);
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if (nr[nreg].mipsReg == IRREG_INVALID || nr[nreg].mipsReg == MIPS_REG_ZERO) {
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// Nothing to do, reg not mapped or mapped to fixed zero.
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_dbg_assert_(!nr[nreg].isDirty);
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return;
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}
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_dbg_assert_(!mr[nr[nreg].mipsReg].isStatic);
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if (mr[nr[nreg].mipsReg].isStatic) {
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ERROR_LOG(JIT, "Cannot FlushNativeReg a statically mapped register");
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return;
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}
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// Multiple mipsRegs may match this if a vector or HI/LO, etc.
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bool isDirty = nr[nreg].isDirty;
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int8_t lanes = 0;
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for (IRReg m = nr[nreg].mipsReg; mr[m].nReg == nreg && m < IRREG_INVALID; ++m) {
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_dbg_assert_(!mr[m].isStatic);
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lanes++;
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}
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if (isDirty) {
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IRReg first = nr[nreg].mipsReg;
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if (mr[first].loc == MIPSLoc::REG_AS_PTR) {
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// We assume this can't be multiple lanes. Maybe some gather craziness?
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_assert_(lanes == 1);
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AdjustNativeRegAsPtr(nreg, false);
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mr[first].loc = MIPSLoc::REG;
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}
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StoreNativeReg(nreg, first, lanes);
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}
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for (int8_t i = 0; i < lanes; ++i) {
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auto &mreg = mr[nr[nreg].mipsReg + i];
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mreg.nReg = -1;
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// Note that it loses its imm status, because imms are always dirty.
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mreg.loc = MIPSLoc::MEM;
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mreg.imm = 0;
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}
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nr[nreg].mipsReg = IRREG_INVALID;
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nr[nreg].isDirty = false;
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nr[nreg].pointerified = false;
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nr[nreg].normalized32 = false;
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}
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void IRNativeRegCacheBase::AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) {
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// This isn't necessary to implement if REG_AS_PTR is unsupported entirely.
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_assert_msg_(false, "AdjustNativeRegAsPtr unimplemented");
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}
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bool IRNativeRegCacheBase::IsValidGPR(IRReg r) const {
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// See MIPSState for these offsets.
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// Don't allow FPU regs, VFPU regs, or VFPU temps here.
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if (r >= 32 && IsValidFPR(r - 32))
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return false;
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// Don't allow nextPC, etc. since it's probably a mistake.
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if (r > IRREG_FPCOND && r != IRREG_LLBIT)
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return false;
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// Don't allow PC either.
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if (r == 241)
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return false;
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return true;
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}
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bool IRNativeRegCacheBase::IsValidGPRNoZero(IRReg r) const {
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return IsValidGPR(r) && r != MIPS_REG_ZERO;
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}
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bool IRNativeRegCacheBase::IsValidFPR(IRReg r) const {
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// FPR parameters are off by 32 within the MIPSState object.
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if (r >= TOTAL_MAPPABLE_IRREGS - 32)
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return false;
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// See MIPSState for these offsets.
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int index = r + 32;
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// Allow FPU or VFPU regs here.
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if (index >= 32 && index < 32 + 32 + 128)
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return true;
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// Also allow VFPU temps.
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if (index >= 224 && index < 224 + 16)
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return true;
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// Nothing else is allowed for the FPU side.
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return false;
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}
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@ -30,6 +30,8 @@ constexpr int TOTAL_MAPPABLE_IRREGS = 256;
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// Arbitrary - increase if your backend has more.
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constexpr int TOTAL_POSSIBLE_NATIVEREGS = 128;
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typedef int8_t IRNativeReg;
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constexpr IRReg IRREG_INVALID = 255;
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class IRWriter;
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@ -75,7 +77,7 @@ private:
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IRWriter *ir_;
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};
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class IRNativeRegCache {
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class IRNativeRegCacheBase {
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protected:
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enum class MIPSLoc {
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// Known immediate value (only in regcache.)
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@ -95,10 +97,10 @@ protected:
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};
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struct RegStatusMIPS {
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// Where is this IR/MIPS register?
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// Where is this IR/MIPS register? Note: base reg if vector.
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MIPSLoc loc = MIPSLoc::MEM;
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// If in a register, what index (into nr array)?
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int8_t nReg = -1;
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IRNativeReg nReg = -1;
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// If a known immediate value, what value?
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uint64_t imm = 0;
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// Locked from spilling (i.e. used by current instruction) as of what IR instruction?
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@ -125,7 +127,9 @@ protected:
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struct StaticAllocation {
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IRReg mr;
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int8_t nr;
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IRNativeReg nr;
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// Register type.
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MIPSLoc loc;
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// Whether the reg should be marked pointerified by default.
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bool pointerified = false;
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// Whether the reg should be considered always normalized at the start of a block.
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@ -133,8 +137,8 @@ protected:
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};
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public:
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IRNativeRegCache(MIPSComp::JitOptions *jo);
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virtual ~IRNativeRegCache() {}
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IRNativeRegCacheBase(MIPSComp::JitOptions *jo);
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virtual ~IRNativeRegCacheBase() {}
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virtual void Start(MIPSComp::IRBlock *irBlock);
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void SetIRIndex(int index) {
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@ -143,13 +147,26 @@ public:
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protected:
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virtual void SetupInitialRegs();
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virtual const StaticAllocation *GetStaticAllocations(int &count) {
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virtual const int *GetAllocationOrder(MIPSLoc type, int &count, int &base) const = 0;
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virtual const StaticAllocation *GetStaticAllocations(int &count) const {
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count = 0;
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return nullptr;
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}
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IRNativeReg AllocateReg(MIPSLoc type);
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IRNativeReg FindFreeReg(MIPSLoc type) const;
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IRNativeReg FindBestToSpill(MIPSLoc type, bool unusedOnly, bool *clobbered) const;
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virtual void DiscardNativeReg(IRNativeReg nreg);
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virtual void FlushNativeReg(IRNativeReg nreg);
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virtual void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state);
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virtual void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) = 0;
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bool IsValidGPR(IRReg r) const;
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bool IsValidGPRNoZero(IRReg r) const;
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bool IsValidFPR(IRReg r) const;
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MIPSComp::JitOptions *jo_;
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MIPSComp::IRBlock *irBlock_ = nullptr;
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const MIPSComp::IRBlock *irBlock_ = nullptr;
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int irIndex_ = 0;
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int totalNativeRegs_ = 0;
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@ -30,7 +30,7 @@ using namespace RiscVGen;
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using namespace RiscVJitConstants;
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RiscVRegCache::RiscVRegCache(MIPSComp::JitOptions *jo)
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: IRNativeRegCache(jo) {
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: IRNativeRegCacheBase(jo) {
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// TODO: Move to using for FPRs and VPRs too?
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totalNativeRegs_ = NUM_RVREG;
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}
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@ -40,7 +40,7 @@ void RiscVRegCache::Init(RiscVEmitter *emitter) {
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}
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void RiscVRegCache::SetupInitialRegs() {
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IRNativeRegCache::SetupInitialRegs();
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IRNativeRegCacheBase::SetupInitialRegs();
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// Treat R_ZERO a bit specially, but it's basically static alloc too.
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nrInitial_[R_ZERO].mipsReg = MIPS_REG_ZERO;
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@ -53,16 +53,18 @@ void RiscVRegCache::SetupInitialRegs() {
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mrInitial_[MIPS_REG_ZERO].isStatic = true;
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}
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const RiscVReg *RiscVRegCache::GetMIPSAllocationOrder(int &count) {
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const int *RiscVRegCache::GetAllocationOrder(MIPSLoc type, int &count, int &base) const {
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_assert_(type == MIPSLoc::REG);
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// X8 and X9 are the most ideal for static alloc because they can be used with compression.
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// Otherwise we stick to saved regs - might not be necessary.
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static const RiscVReg allocationOrder[] = {
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static const int allocationOrder[] = {
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X8, X9, X12, X13, X14, X15, X5, X6, X7, X16, X17, X18, X19, X20, X21, X22, X23, X28, X29, X30, X31,
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};
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static const RiscVReg allocationOrderStaticAlloc[] = {
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static const int allocationOrderStaticAlloc[] = {
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X12, X13, X14, X15, X5, X6, X7, X16, X17, X21, X22, X23, X28, X29, X30, X31,
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};
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base = X0;
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if (jo_->useStaticAlloc) {
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count = ARRAY_SIZE(allocationOrderStaticAlloc);
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return allocationOrderStaticAlloc;
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@ -72,20 +74,20 @@ const RiscVReg *RiscVRegCache::GetMIPSAllocationOrder(int &count) {
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}
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}
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const RiscVRegCache::StaticAllocation *RiscVRegCache::GetStaticAllocations(int &count) {
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const RiscVRegCache::StaticAllocation *RiscVRegCache::GetStaticAllocations(int &count) const {
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static const StaticAllocation allocs[] = {
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{ MIPS_REG_SP, X8, true },
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{ MIPS_REG_V0, X9 },
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{ MIPS_REG_V1, X18 },
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{ MIPS_REG_A0, X19 },
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{ MIPS_REG_RA, X20 },
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{ MIPS_REG_SP, X8, MIPSLoc::REG, true },
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{ MIPS_REG_V0, X9, MIPSLoc::REG },
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{ MIPS_REG_V1, X18, MIPSLoc::REG },
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{ MIPS_REG_A0, X19, MIPSLoc::REG },
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{ MIPS_REG_RA, X20, MIPSLoc::REG },
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};
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if (jo_->useStaticAlloc) {
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count = ARRAY_SIZE(allocs);
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return allocs;
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}
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return IRNativeRegCache::GetStaticAllocations(count);
|
||||
return IRNativeRegCacheBase::GetStaticAllocations(count);
|
||||
}
|
||||
|
||||
void RiscVRegCache::EmitLoadStaticRegisters() {
|
||||
@ -115,28 +117,28 @@ void RiscVRegCache::EmitSaveStaticRegisters() {
|
||||
void RiscVRegCache::FlushBeforeCall() {
|
||||
// These registers are not preserved by function calls.
|
||||
for (int i = 5; i <= 7; ++i) {
|
||||
FlushRiscVReg(RiscVReg(X0 + i));
|
||||
FlushNativeReg(i);
|
||||
}
|
||||
for (int i = 10; i <= 17; ++i) {
|
||||
FlushRiscVReg(RiscVReg(X0 + i));
|
||||
FlushNativeReg(i);
|
||||
}
|
||||
for (int i = 28; i <= 31; ++i) {
|
||||
FlushRiscVReg(RiscVReg(X0 + i));
|
||||
FlushNativeReg(i);
|
||||
}
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsInRAM(IRReg reg) {
|
||||
_dbg_assert_(IsValidReg(reg));
|
||||
_dbg_assert_(IsValidGPR(reg));
|
||||
return mr[reg].loc == MIPSLoc::MEM;
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsMapped(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
return mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM;
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsMappedAsPointer(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
if (mr[mipsReg].loc == MIPSLoc::REG) {
|
||||
return nr[mr[mipsReg].nReg].pointerified;
|
||||
} else if (mr[mipsReg].loc == MIPSLoc::REG_IMM) {
|
||||
@ -157,7 +159,7 @@ bool RiscVRegCache::IsMappedAsStaticPointer(IRReg reg) {
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsNormalized32(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
if (XLEN == 32)
|
||||
return true;
|
||||
if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) {
|
||||
@ -196,7 +198,7 @@ void RiscVRegCache::MarkPtrDirty(RiscVReg reg) {
|
||||
}
|
||||
|
||||
RiscVGen::RiscVReg RiscVRegCache::Normalize32(IRReg mipsReg, RiscVGen::RiscVReg destReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
_dbg_assert_(destReg == INVALID_REG || (destReg > X0 && destReg <= X31));
|
||||
|
||||
RiscVReg reg = (RiscVReg)mr[mipsReg].nReg;
|
||||
@ -257,7 +259,7 @@ void RiscVRegCache::SetRegImm(RiscVReg reg, u64 imm) {
|
||||
|
||||
void RiscVRegCache::MapRegTo(RiscVReg reg, IRReg mipsReg, MIPSMap mapFlags) {
|
||||
_dbg_assert_(reg > X0 && reg <= X31);
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
_dbg_assert_(!mr[mipsReg].isStatic);
|
||||
if (mr[mipsReg].isStatic) {
|
||||
ERROR_LOG(JIT, "Cannot MapRegTo static register %d", mipsReg);
|
||||
@ -316,88 +318,8 @@ void RiscVRegCache::MapRegTo(RiscVReg reg, IRReg mipsReg, MIPSMap mapFlags) {
|
||||
mr[mipsReg].nReg = reg;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::AllocateReg() {
|
||||
int allocCount;
|
||||
const RiscVReg *allocOrder = GetMIPSAllocationOrder(allocCount);
|
||||
|
||||
allocate:
|
||||
for (int i = 0; i < allocCount; i++) {
|
||||
RiscVReg reg = allocOrder[i];
|
||||
|
||||
if (nr[reg].mipsReg == IRREG_INVALID && nr[reg].tempLockIRIndex < irIndex_) {
|
||||
return reg;
|
||||
}
|
||||
}
|
||||
|
||||
// Still nothing. Let's spill a reg and goto 10.
|
||||
bool clobbered;
|
||||
RiscVReg bestToSpill = FindBestToSpill(true, &clobbered);
|
||||
if (bestToSpill == INVALID_REG) {
|
||||
bestToSpill = FindBestToSpill(false, &clobbered);
|
||||
}
|
||||
|
||||
if (bestToSpill != INVALID_REG) {
|
||||
if (clobbered) {
|
||||
DiscardR(nr[bestToSpill].mipsReg);
|
||||
} else {
|
||||
FlushRiscVReg(bestToSpill);
|
||||
}
|
||||
// Now one must be free.
|
||||
goto allocate;
|
||||
}
|
||||
|
||||
// Uh oh, we have all of them spilllocked....
|
||||
ERROR_LOG_REPORT(JIT, "Out of spillable registers in block PC %08x, index %d", irBlock_->GetOriginalStart(), irIndex_);
|
||||
_assert_(bestToSpill != INVALID_REG);
|
||||
return INVALID_REG;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::FindBestToSpill(bool unusedOnly, bool *clobbered) {
|
||||
int allocCount;
|
||||
const RiscVReg *allocOrder = GetMIPSAllocationOrder(allocCount);
|
||||
|
||||
static const int UNUSED_LOOKAHEAD_OPS = 30;
|
||||
|
||||
IRSituation info;
|
||||
info.lookaheadCount = UNUSED_LOOKAHEAD_OPS;
|
||||
info.currentIndex = irIndex_;
|
||||
info.instructions = irBlock_->GetInstructions();
|
||||
info.numInstructions = irBlock_->GetNumInstructions();
|
||||
|
||||
*clobbered = false;
|
||||
for (int i = 0; i < allocCount; i++) {
|
||||
RiscVReg reg = allocOrder[i];
|
||||
if (nr[reg].mipsReg != IRREG_INVALID && mr[nr[reg].mipsReg].spillLockIRIndex >= irIndex_)
|
||||
continue;
|
||||
if (nr[reg].tempLockIRIndex >= irIndex_)
|
||||
continue;
|
||||
|
||||
// As it's in alloc-order, we know it's not static so we don't need to check for that.
|
||||
IRUsage usage = IRNextGPRUsage(nr[reg].mipsReg, info);
|
||||
|
||||
// Awesome, a clobbered reg. Let's use it.
|
||||
if (usage == IRUsage::CLOBBERED) {
|
||||
// TODO: Check HI/LO clobber together if we combine.
|
||||
bool canClobber = true;
|
||||
if (canClobber) {
|
||||
*clobbered = true;
|
||||
return reg;
|
||||
}
|
||||
}
|
||||
|
||||
// Not awesome. A used reg. Let's try to avoid spilling.
|
||||
if (!unusedOnly || usage == IRUsage::UNUSED) {
|
||||
// TODO: Use age or something to choose which register to spill?
|
||||
// TODO: Spill dirty regs first? or opposite?
|
||||
return reg;
|
||||
}
|
||||
}
|
||||
|
||||
return INVALID_REG;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::TryMapTempImm(IRReg r) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidGPR(r));
|
||||
// If already mapped, no need for a temporary.
|
||||
if (IsMapped(r)) {
|
||||
return R(r);
|
||||
@ -421,7 +343,7 @@ RiscVReg RiscVRegCache::TryMapTempImm(IRReg r) {
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::GetAndLockTempR() {
|
||||
RiscVReg reg = AllocateReg();
|
||||
RiscVReg reg = (RiscVReg)AllocateReg(MIPSLoc::REG);
|
||||
if (reg != INVALID_REG) {
|
||||
nr[reg].tempLockIRIndex = irIndex_;
|
||||
}
|
||||
@ -429,7 +351,7 @@ RiscVReg RiscVRegCache::GetAndLockTempR() {
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::MapReg(IRReg mipsReg, MIPSMap mapFlags) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
|
||||
// TODO: Optimization to force HI/LO to be combined?
|
||||
|
||||
@ -521,7 +443,7 @@ RiscVReg RiscVRegCache::MapReg(IRReg mipsReg, MIPSMap mapFlags) {
|
||||
}
|
||||
|
||||
// Okay, not mapped, so we need to allocate an RV register.
|
||||
RiscVReg reg = AllocateReg();
|
||||
RiscVReg reg = (RiscVReg)AllocateReg(MIPSLoc::REG);
|
||||
if (reg != INVALID_REG) {
|
||||
// Grab it, and load the value into it (if requested).
|
||||
MapRegTo(reg, mipsReg, mapFlags);
|
||||
@ -531,7 +453,7 @@ RiscVReg RiscVRegCache::MapReg(IRReg mipsReg, MIPSMap mapFlags) {
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::MapRegAsPointer(IRReg reg) {
|
||||
_dbg_assert_(IsValidRegNoZero(reg));
|
||||
_dbg_assert_(IsValidGPRNoZero(reg));
|
||||
|
||||
// Already mapped.
|
||||
if (mr[reg].loc == MIPSLoc::REG_AS_PTR) {
|
||||
@ -639,83 +561,38 @@ void RiscVRegCache::MapDirtyDirtyInIn(IRReg rd1, IRReg rd2, IRReg rs, IRReg rt,
|
||||
ReleaseSpillLock(rd1, rd2, rs, rt);
|
||||
}
|
||||
|
||||
void RiscVRegCache::FlushRiscVReg(RiscVReg r) {
|
||||
_dbg_assert_(r > X0 && r <= X31);
|
||||
_dbg_assert_(nr[r].mipsReg != MIPS_REG_ZERO);
|
||||
if (r == INVALID_REG) {
|
||||
ERROR_LOG(JIT, "FlushRiscVReg called on invalid register %d", r);
|
||||
return;
|
||||
}
|
||||
if (nr[r].mipsReg == IRREG_INVALID) {
|
||||
// Nothing to do, reg not mapped.
|
||||
_dbg_assert_(!nr[r].isDirty);
|
||||
return;
|
||||
}
|
||||
_dbg_assert_(!mr[nr[r].mipsReg].isStatic);
|
||||
if (mr[nr[r].mipsReg].isStatic) {
|
||||
ERROR_LOG(JIT, "Cannot FlushRiscVReg a statically mapped register");
|
||||
return;
|
||||
}
|
||||
auto &mreg = mr[nr[r].mipsReg];
|
||||
if (mreg.loc == MIPSLoc::REG_IMM || nr[r].mipsReg == MIPS_REG_ZERO) {
|
||||
// We know its immediate value, no need to STR now.
|
||||
mreg.loc = MIPSLoc::IMM;
|
||||
mreg.nReg = (int)INVALID_REG;
|
||||
void RiscVRegCache::AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) {
|
||||
RiscVReg r = (RiscVReg)(X0 + nreg);
|
||||
if (state) {
|
||||
AddMemBase(r);
|
||||
} else {
|
||||
if (mreg.loc == MIPSLoc::IMM || nr[r].isDirty) {
|
||||
if (mreg.loc == MIPSLoc::REG_AS_PTR) {
|
||||
// Unpointerify, in case dirty.
|
||||
#ifdef MASKED_PSP_MEMORY
|
||||
_dbg_assert_(!nr[r].isDirty);
|
||||
_dbg_assert_(!nr[nreg].isDirty);
|
||||
#endif
|
||||
emit_->SUB(r, r, MEMBASEREG);
|
||||
mreg.loc = MIPSLoc::REG;
|
||||
nr[r].normalized32 = false;
|
||||
}
|
||||
RiscVReg storeReg = RiscVRegForFlush(nr[r].mipsReg);
|
||||
if (storeReg != INVALID_REG)
|
||||
emit_->SW(storeReg, CTXREG, GetMipsRegOffset(nr[r].mipsReg));
|
||||
}
|
||||
mreg.loc = MIPSLoc::MEM;
|
||||
mreg.nReg = (int)INVALID_REG;
|
||||
mreg.imm = -1;
|
||||
emit_->SUB(r, r, MEMBASEREG);
|
||||
nr[nreg].normalized32 = false;
|
||||
}
|
||||
nr[r].isDirty = false;
|
||||
nr[r].mipsReg = IRREG_INVALID;
|
||||
nr[r].pointerified = false;
|
||||
}
|
||||
|
||||
void RiscVRegCache::StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) {
|
||||
RiscVReg r = (RiscVReg)(X0 + nreg);
|
||||
_dbg_assert_(r > X0 && r <= X31);
|
||||
_dbg_assert_(first != MIPS_REG_ZERO);
|
||||
// Multilane not yet supported.
|
||||
_assert_(lanes == 1);
|
||||
_assert_(mr[first].loc == MIPSLoc::REG || mr[first].loc == MIPSLoc::REG_IMM);
|
||||
emit_->SW(r, CTXREG, GetMipsRegOffset(first));
|
||||
}
|
||||
|
||||
void RiscVRegCache::DiscardR(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidRegNoZero(mipsReg));
|
||||
_dbg_assert_(IsValidGPRNoZero(mipsReg));
|
||||
if (mr[mipsReg].isStatic) {
|
||||
// Simply do nothing unless it's an IMM/RVREG_IMM/RVREG_AS_PTR, in case we just switch it over to RVREG, losing the value.
|
||||
RiscVReg riscvReg = (RiscVReg)mr[mipsReg].nReg;
|
||||
_dbg_assert_(riscvReg != INVALID_REG);
|
||||
if (mipsReg == MIPS_REG_ZERO) {
|
||||
// Shouldn't happen, but in case it does.
|
||||
mr[mipsReg].loc = MIPSLoc::REG_IMM;
|
||||
mr[mipsReg].nReg = R_ZERO;
|
||||
mr[mipsReg].imm = 0;
|
||||
} else if (mr[mipsReg].loc == MIPSLoc::REG_IMM || mr[mipsReg].loc == MIPSLoc::IMM || mr[mipsReg].loc == MIPSLoc::REG_AS_PTR) {
|
||||
// Ignore the imm value, restore sanity
|
||||
mr[mipsReg].loc = MIPSLoc::REG;
|
||||
nr[riscvReg].pointerified = false;
|
||||
nr[riscvReg].isDirty = false;
|
||||
nr[riscvReg].normalized32 = false;
|
||||
}
|
||||
DiscardNativeReg(mr[mipsReg].nReg);
|
||||
return;
|
||||
}
|
||||
const MIPSLoc prevLoc = mr[mipsReg].loc;
|
||||
if (prevLoc == MIPSLoc::REG || prevLoc == MIPSLoc::REG_IMM || prevLoc == MIPSLoc::REG_AS_PTR) {
|
||||
RiscVReg riscvReg = (RiscVReg)mr[mipsReg].nReg;
|
||||
_dbg_assert_(riscvReg != INVALID_REG);
|
||||
nr[riscvReg].mipsReg = IRREG_INVALID;
|
||||
nr[riscvReg].pointerified = false;
|
||||
nr[riscvReg].isDirty = false;
|
||||
nr[riscvReg].normalized32 = false;
|
||||
mr[mipsReg].nReg = (int)INVALID_REG;
|
||||
mr[mipsReg].loc = MIPSLoc::MEM;
|
||||
mr[mipsReg].imm = -1;
|
||||
DiscardNativeReg(mr[mipsReg].nReg);
|
||||
}
|
||||
if (prevLoc == MIPSLoc::IMM && mipsReg != MIPS_REG_ZERO) {
|
||||
mr[mipsReg].loc = MIPSLoc::MEM;
|
||||
@ -724,7 +601,7 @@ void RiscVRegCache::DiscardR(IRReg mipsReg) {
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::RiscVRegForFlush(IRReg r) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidGPR(r));
|
||||
if (mr[r].isStatic)
|
||||
return INVALID_REG; // No flushing needed
|
||||
|
||||
@ -772,7 +649,7 @@ RiscVReg RiscVRegCache::RiscVRegForFlush(IRReg r) {
|
||||
}
|
||||
|
||||
void RiscVRegCache::FlushR(IRReg r) {
|
||||
_dbg_assert_(IsValidRegNoZero(r));
|
||||
_dbg_assert_(IsValidGPRNoZero(r));
|
||||
if (mr[r].isStatic) {
|
||||
ERROR_LOG(JIT, "Cannot flush static reg %d", r);
|
||||
return;
|
||||
@ -796,10 +673,7 @@ void RiscVRegCache::FlushR(IRReg r) {
|
||||
case MIPSLoc::REG:
|
||||
case MIPSLoc::REG_IMM:
|
||||
if (nr[mr[r].nReg].isDirty) {
|
||||
RiscVReg storeReg = RiscVRegForFlush(r);
|
||||
if (storeReg != INVALID_REG) {
|
||||
emit_->SW(storeReg, CTXREG, GetMipsRegOffset(r));
|
||||
}
|
||||
StoreNativeReg(mr[r].nReg, r, 1);
|
||||
nr[mr[r].nReg].isDirty = false;
|
||||
}
|
||||
nr[mr[r].nReg].mipsReg = IRREG_INVALID;
|
||||
@ -808,17 +682,10 @@ void RiscVRegCache::FlushR(IRReg r) {
|
||||
|
||||
case MIPSLoc::REG_AS_PTR:
|
||||
if (nr[mr[r].nReg].isDirty) {
|
||||
#ifdef MASKED_PSP_MEMORY
|
||||
// This is kinda bad, because we've cleared bits in it.
|
||||
_dbg_assert_(!nr[mr[r].nReg].isDirty);
|
||||
#endif
|
||||
emit_->SUB((RiscVReg)mr[r].nReg, (RiscVReg)mr[r].nReg, MEMBASEREG);
|
||||
// We set this so RiscVRegForFlush knows it's no longer a pointer.
|
||||
AdjustNativeRegAsPtr(mr[r].nReg, false);
|
||||
// We set this so StoreNativeReg knows it's no longer a pointer.
|
||||
mr[r].loc = MIPSLoc::REG;
|
||||
RiscVReg storeReg = RiscVRegForFlush(r);
|
||||
if (storeReg != INVALID_REG) {
|
||||
emit_->SW(storeReg, CTXREG, GetMipsRegOffset(r));
|
||||
}
|
||||
StoreNativeReg(mr[r].nReg, r, 1);
|
||||
nr[mr[r].nReg].isDirty = false;
|
||||
}
|
||||
nr[mr[r].nReg].mipsReg = IRREG_INVALID;
|
||||
@ -845,11 +712,10 @@ void RiscVRegCache::FlushR(IRReg r) {
|
||||
|
||||
void RiscVRegCache::FlushAll() {
|
||||
// Note: make sure not to change the registers when flushing:
|
||||
// Branching code expects the armreg to retain its value.
|
||||
// Branching code expects the native reg to retain its value.
|
||||
|
||||
// TODO: HI/LO optimization?
|
||||
|
||||
// Final pass to grab any that were left behind.
|
||||
for (int i = 1; i < TOTAL_MAPPABLE_IRREGS; i++) {
|
||||
IRReg mipsReg = IRReg(i);
|
||||
if (mr[i].isStatic) {
|
||||
@ -878,7 +744,7 @@ void RiscVRegCache::FlushAll() {
|
||||
ERROR_LOG(JIT, "RV reg of static %i is invalid", i);
|
||||
continue;
|
||||
}
|
||||
} else if (IsValidRegNoZero(mipsReg)) {
|
||||
} else if (IsValidGPRNoZero(mipsReg)) {
|
||||
FlushR(mipsReg);
|
||||
}
|
||||
}
|
||||
@ -907,7 +773,7 @@ void RiscVRegCache::FlushAll() {
|
||||
}
|
||||
|
||||
void RiscVRegCache::SetImm(IRReg r, u64 immVal) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidGPR(r));
|
||||
if (r == MIPS_REG_ZERO && immVal != 0) {
|
||||
ERROR_LOG_REPORT(JIT, "Trying to set immediate %08x to r0", (u32)immVal);
|
||||
return;
|
||||
@ -943,7 +809,7 @@ void RiscVRegCache::SetImm(IRReg r, u64 immVal) {
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsImm(IRReg r) const {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidGPR(r));
|
||||
if (r == MIPS_REG_ZERO)
|
||||
return true;
|
||||
else
|
||||
@ -951,7 +817,7 @@ bool RiscVRegCache::IsImm(IRReg r) const {
|
||||
}
|
||||
|
||||
u64 RiscVRegCache::GetImm(IRReg r) const {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidGPR(r));
|
||||
if (r == MIPS_REG_ZERO)
|
||||
return 0;
|
||||
if (mr[r].loc != MIPSLoc::IMM && mr[r].loc != MIPSLoc::REG_IMM) {
|
||||
@ -961,41 +827,15 @@ u64 RiscVRegCache::GetImm(IRReg r) const {
|
||||
}
|
||||
|
||||
int RiscVRegCache::GetMipsRegOffset(IRReg r) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidGPR(r));
|
||||
return r * 4;
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsValidReg(IRReg r) const {
|
||||
if (r < 0 || r >= TOTAL_MAPPABLE_IRREGS)
|
||||
return false;
|
||||
|
||||
// See MIPSState for these offsets.
|
||||
|
||||
// Don't allow FPU or VFPU regs here.
|
||||
if (r >= 32 && r < 32 + 32 + 128)
|
||||
return false;
|
||||
// Also disallow VFPU temps.
|
||||
if (r >= 224 && r < 224 + 16)
|
||||
return false;
|
||||
// Don't allow nextPC, etc. since it's probably a mistake.
|
||||
if (r > IRREG_FPCOND && r != IRREG_LLBIT)
|
||||
return false;
|
||||
// Don't allow PC either.
|
||||
if (r == 241)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool RiscVRegCache::IsValidRegNoZero(IRReg r) const {
|
||||
return IsValidReg(r) && r != MIPS_REG_ZERO;
|
||||
}
|
||||
|
||||
void RiscVRegCache::SpillLock(IRReg r1, IRReg r2, IRReg r3, IRReg r4) {
|
||||
_dbg_assert_(IsValidReg(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidReg(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidReg(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidReg(r4));
|
||||
_dbg_assert_(IsValidGPR(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidGPR(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidGPR(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidGPR(r4));
|
||||
mr[r1].spillLockIRIndex = irIndex_;
|
||||
if (r2 != IRREG_INVALID) mr[r2].spillLockIRIndex = irIndex_;
|
||||
if (r3 != IRREG_INVALID) mr[r3].spillLockIRIndex = irIndex_;
|
||||
@ -1003,10 +843,10 @@ void RiscVRegCache::SpillLock(IRReg r1, IRReg r2, IRReg r3, IRReg r4) {
|
||||
}
|
||||
|
||||
void RiscVRegCache::ReleaseSpillLock(IRReg r1, IRReg r2, IRReg r3, IRReg r4) {
|
||||
_dbg_assert_(IsValidReg(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidReg(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidReg(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidReg(r4));
|
||||
_dbg_assert_(IsValidGPR(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidGPR(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidGPR(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidGPR(r4));
|
||||
if (!mr[r1].isStatic)
|
||||
mr[r1].spillLockIRIndex = -1;
|
||||
if (r2 != IRREG_INVALID && !mr[r2].isStatic)
|
||||
@ -1018,7 +858,7 @@ void RiscVRegCache::ReleaseSpillLock(IRReg r1, IRReg r2, IRReg r3, IRReg r4) {
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::R(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
_dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM);
|
||||
if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) {
|
||||
return (RiscVReg)mr[mipsReg].nReg;
|
||||
@ -1029,7 +869,7 @@ RiscVReg RiscVRegCache::R(IRReg mipsReg) {
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCache::RPtr(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(IsValidGPR(mipsReg));
|
||||
_dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM || mr[mipsReg].loc == MIPSLoc::REG_AS_PTR);
|
||||
if (mr[mipsReg].loc == MIPSLoc::REG_AS_PTR) {
|
||||
return (RiscVReg)mr[mipsReg].nReg;
|
||||
|
||||
@ -57,7 +57,7 @@ enum class MapType {
|
||||
|
||||
} // namespace RiscVJitConstants
|
||||
|
||||
class RiscVRegCache : public IRNativeRegCache {
|
||||
class RiscVRegCache : public IRNativeRegCacheBase {
|
||||
public:
|
||||
RiscVRegCache(MIPSComp::JitOptions *jo);
|
||||
|
||||
@ -98,7 +98,6 @@ public:
|
||||
void FlushBeforeCall();
|
||||
void FlushAll();
|
||||
void FlushR(IRReg r);
|
||||
void FlushRiscVReg(RiscVGen::RiscVReg r);
|
||||
void DiscardR(IRReg r);
|
||||
|
||||
RiscVGen::RiscVReg GetAndLockTempR();
|
||||
@ -112,21 +111,18 @@ public:
|
||||
|
||||
protected:
|
||||
void SetupInitialRegs() override;
|
||||
const StaticAllocation *GetStaticAllocations(int &count) override;
|
||||
const StaticAllocation *GetStaticAllocations(int &count) const override;
|
||||
const int *GetAllocationOrder(MIPSLoc type, int &count, int &base) const override;
|
||||
void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override;
|
||||
void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
|
||||
|
||||
private:
|
||||
const RiscVGen::RiscVReg *GetMIPSAllocationOrder(int &count);
|
||||
void MapRegTo(RiscVGen::RiscVReg reg, IRReg mipsReg, RiscVJitConstants::MIPSMap mapFlags);
|
||||
RiscVGen::RiscVReg AllocateReg();
|
||||
RiscVGen::RiscVReg FindBestToSpill(bool unusedOnly, bool *clobbered);
|
||||
RiscVGen::RiscVReg RiscVRegForFlush(IRReg r);
|
||||
void SetRegImm(RiscVGen::RiscVReg reg, u64 imm);
|
||||
void AddMemBase(RiscVGen::RiscVReg reg);
|
||||
int GetMipsRegOffset(IRReg r);
|
||||
|
||||
bool IsValidReg(IRReg r) const;
|
||||
bool IsValidRegNoZero(IRReg r) const;
|
||||
|
||||
RiscVGen::RiscVEmitter *emit_ = nullptr;
|
||||
|
||||
enum {
|
||||
|
||||
@ -30,7 +30,7 @@ using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
RiscVRegCacheFPU::RiscVRegCacheFPU(MIPSComp::JitOptions *jo)
|
||||
: IRNativeRegCache(jo) {
|
||||
: IRNativeRegCacheBase(jo) {
|
||||
totalNativeRegs_ = NUM_RVFPUREG;
|
||||
}
|
||||
|
||||
@ -38,137 +38,65 @@ void RiscVRegCacheFPU::Init(RiscVEmitter *emitter) {
|
||||
emit_ = emitter;
|
||||
}
|
||||
|
||||
const RiscVReg *RiscVRegCacheFPU::GetMIPSAllocationOrder(int &count) {
|
||||
const int *RiscVRegCacheFPU::GetAllocationOrder(MIPSLoc type, int &count, int &base) const {
|
||||
_assert_(type == MIPSLoc::FREG);
|
||||
// F8 through F15 are used for compression, so they are great.
|
||||
// TODO: Maybe we could remove some saved regs since we rarely need that many? Or maybe worth it?
|
||||
static const RiscVReg allocationOrder[] = {
|
||||
static const int allocationOrder[] = {
|
||||
F8, F9, F10, F11, F12, F13, F14, F15,
|
||||
F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,
|
||||
};
|
||||
|
||||
count = ARRAY_SIZE(allocationOrder);
|
||||
base = F0;
|
||||
return allocationOrder;
|
||||
}
|
||||
|
||||
bool RiscVRegCacheFPU::IsInRAM(IRReg reg) {
|
||||
_dbg_assert_(IsValidReg(reg));
|
||||
return mr[reg].loc == MIPSLoc::MEM;
|
||||
_dbg_assert_(IsValidFPR(reg));
|
||||
return mr[reg + 32].loc == MIPSLoc::MEM;
|
||||
}
|
||||
|
||||
bool RiscVRegCacheFPU::IsMapped(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
return mr[mipsReg].loc == MIPSLoc::FREG;
|
||||
_dbg_assert_(IsValidFPR(mipsReg));
|
||||
return mr[mipsReg + 32].loc == MIPSLoc::FREG;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCacheFPU::MapReg(IRReg mipsReg, MIPSMap mapFlags) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(mr[mipsReg].loc == MIPSLoc::MEM || mr[mipsReg].loc == MIPSLoc::FREG);
|
||||
_dbg_assert_(IsValidFPR(mipsReg));
|
||||
_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);
|
||||
|
||||
pendingFlush_ = true;
|
||||
|
||||
// Let's see if it's already mapped. If so we just need to update the dirty flag.
|
||||
// We don't need to check for NOINIT because we assume that anyone who maps
|
||||
// with that flag immediately writes a "known" value to the register.
|
||||
if (mr[mipsReg].loc == MIPSLoc::FREG) {
|
||||
_assert_msg_(nr[mr[mipsReg].nReg].mipsReg == mipsReg, "GPU mapping out of sync, IR=%i", mipsReg);
|
||||
if (mr[mipsReg + 32].loc == MIPSLoc::FREG) {
|
||||
_assert_msg_(nr[mr[mipsReg + 32].nReg].mipsReg == mipsReg + 32, "FPR mapping out of sync, IR=%i", mipsReg);
|
||||
if ((mapFlags & MIPSMap::DIRTY) == MIPSMap::DIRTY) {
|
||||
nr[mr[mipsReg].nReg].isDirty = true;
|
||||
nr[mr[mipsReg + 32].nReg].isDirty = true;
|
||||
}
|
||||
return (RiscVReg)(mr[mipsReg].nReg + F0);
|
||||
return (RiscVReg)(mr[mipsReg + 32].nReg + F0);
|
||||
}
|
||||
|
||||
// Okay, not mapped, so we need to allocate an RV register.
|
||||
RiscVReg reg = AllocateReg();
|
||||
if (reg != INVALID_REG) {
|
||||
IRNativeReg nreg = AllocateReg(MIPSLoc::FREG);
|
||||
if (nreg != -1) {
|
||||
// That means it's free. Grab it, and load the value into it (if requested).
|
||||
nr[reg - F0].isDirty = (mapFlags & MIPSMap::DIRTY) == MIPSMap::DIRTY;
|
||||
nr[nreg].isDirty = (mapFlags & MIPSMap::DIRTY) == MIPSMap::DIRTY;
|
||||
if ((mapFlags & MIPSMap::NOINIT) != MIPSMap::NOINIT) {
|
||||
if (mr[mipsReg].loc == MIPSLoc::MEM) {
|
||||
emit_->FL(32, reg, CTXREG, GetMipsRegOffset(mipsReg));
|
||||
if (mr[mipsReg + 32].loc == MIPSLoc::MEM) {
|
||||
emit_->FL(32, (RiscVReg)(F0 + nreg), CTXREG, GetMipsRegOffset(mipsReg + 32));
|
||||
}
|
||||
}
|
||||
nr[reg - F0].mipsReg = mipsReg;
|
||||
mr[mipsReg].loc = MIPSLoc::FREG;
|
||||
mr[mipsReg].nReg = reg - F0;
|
||||
return reg;
|
||||
nr[nreg].mipsReg = mipsReg + 32;
|
||||
mr[mipsReg + 32].loc = MIPSLoc::FREG;
|
||||
mr[mipsReg + 32].nReg = nreg;
|
||||
return (RiscVReg)(F0 + nreg);
|
||||
}
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCacheFPU::AllocateReg() {
|
||||
int allocCount = 0;
|
||||
const RiscVReg *allocOrder = GetMIPSAllocationOrder(allocCount);
|
||||
|
||||
allocate:
|
||||
for (int i = 0; i < allocCount; i++) {
|
||||
RiscVReg reg = allocOrder[i];
|
||||
|
||||
if (nr[reg - F0].mipsReg == IRREG_INVALID) {
|
||||
return reg;
|
||||
}
|
||||
}
|
||||
|
||||
// Still nothing. Let's spill a reg and goto 10.
|
||||
bool clobbered;
|
||||
RiscVReg bestToSpill = FindBestToSpill(true, &clobbered);
|
||||
if (bestToSpill == INVALID_REG) {
|
||||
bestToSpill = FindBestToSpill(false, &clobbered);
|
||||
}
|
||||
|
||||
if (bestToSpill != INVALID_REG) {
|
||||
if (clobbered) {
|
||||
DiscardR(nr[bestToSpill - F0].mipsReg);
|
||||
} else {
|
||||
FlushRiscVReg(bestToSpill);
|
||||
}
|
||||
// Now one must be free.
|
||||
goto allocate;
|
||||
}
|
||||
|
||||
// Uh oh, we have all of them spilllocked....
|
||||
ERROR_LOG_REPORT(JIT, "Out of spillable registers in block PC %08x, index %d", irBlock_->GetOriginalStart(), irIndex_);
|
||||
_assert_(bestToSpill != INVALID_REG);
|
||||
return INVALID_REG;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCacheFPU::FindBestToSpill(bool unusedOnly, bool *clobbered) {
|
||||
int allocCount = 0;
|
||||
const RiscVReg *allocOrder = GetMIPSAllocationOrder(allocCount);
|
||||
|
||||
static const int UNUSED_LOOKAHEAD_OPS = 30;
|
||||
|
||||
IRSituation info;
|
||||
info.lookaheadCount = UNUSED_LOOKAHEAD_OPS;
|
||||
info.currentIndex = irIndex_;
|
||||
info.instructions = irBlock_->GetInstructions();
|
||||
info.numInstructions = irBlock_->GetNumInstructions();
|
||||
|
||||
*clobbered = false;
|
||||
for (int i = 0; i < allocCount; i++) {
|
||||
RiscVReg reg = allocOrder[i];
|
||||
if (nr[reg - F0].mipsReg != IRREG_INVALID && mr[nr[reg - F0].mipsReg].spillLockIRIndex >= irIndex_)
|
||||
continue;
|
||||
|
||||
// As it's in alloc-order, we know it's not static so we don't need to check for that.
|
||||
IRUsage usage = IRNextFPRUsage(nr[reg - F0].mipsReg, info);
|
||||
|
||||
// Awesome, a clobbered reg. Let's use it.
|
||||
if (usage == IRUsage::CLOBBERED) {
|
||||
*clobbered = true;
|
||||
return reg;
|
||||
}
|
||||
|
||||
// Not awesome. A used reg. Let's try to avoid spilling.
|
||||
if (!unusedOnly || usage == IRUsage::UNUSED) {
|
||||
// TODO: Use age or something to choose which register to spill?
|
||||
// TODO: Spill dirty regs first? or opposite?
|
||||
return reg;
|
||||
}
|
||||
}
|
||||
|
||||
return INVALID_REG;
|
||||
return (RiscVReg)(F0 + nreg);
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::MapInIn(IRReg rd, IRReg rs) {
|
||||
@ -200,7 +128,7 @@ RiscVReg RiscVRegCacheFPU::MapDirtyInTemp(IRReg rd, IRReg rs, bool avoidLoad) {
|
||||
bool load = !avoidLoad || rd == rs;
|
||||
MapReg(rd, load ? MIPSMap::DIRTY : MIPSMap::NOINIT);
|
||||
MapReg(rs);
|
||||
RiscVReg temp = AllocateReg();
|
||||
RiscVReg temp = (RiscVReg)(F0 + AllocateReg(MIPSLoc::FREG));
|
||||
ReleaseSpillLock(rd, rs);
|
||||
return temp;
|
||||
}
|
||||
@ -239,44 +167,40 @@ RiscVReg RiscVRegCacheFPU::Map4DirtyInTemp(IRReg rdbase, IRReg rsbase, bool avoi
|
||||
MapReg(rdbase + i, load ? MIPSMap::DIRTY : MIPSMap::NOINIT);
|
||||
for (int i = 0; i < 4; ++i)
|
||||
MapReg(rsbase + i);
|
||||
RiscVReg temp = AllocateReg();
|
||||
RiscVReg temp = (RiscVReg)(F0 + AllocateReg(MIPSLoc::FREG));
|
||||
for (int i = 0; i < 4; ++i)
|
||||
ReleaseSpillLock(rdbase + i, rsbase + i);
|
||||
return temp;
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::FlushRiscVReg(RiscVReg r) {
|
||||
void RiscVRegCacheFPU::StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) {
|
||||
RiscVReg r = (RiscVReg)(F0 + nreg);
|
||||
_dbg_assert_(r >= F0 && r <= F31);
|
||||
int reg = r - F0;
|
||||
if (nr[reg].mipsReg == IRREG_INVALID) {
|
||||
// Nothing to do, reg not mapped.
|
||||
return;
|
||||
// Multilane not yet supported.
|
||||
_assert_(lanes == 1);
|
||||
if (mr[first].loc == MIPSLoc::FREG) {
|
||||
emit_->FS(32, r, CTXREG, GetMipsRegOffset(first));
|
||||
} else {
|
||||
_assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot store this type: %d", (int)mr[first].loc);
|
||||
}
|
||||
if (nr[reg].isDirty && mr[nr[reg].mipsReg].loc == MIPSLoc::FREG) {
|
||||
emit_->FS(32, r, CTXREG, GetMipsRegOffset(nr[reg].mipsReg));
|
||||
}
|
||||
mr[nr[reg].mipsReg].loc = MIPSLoc::MEM;
|
||||
mr[nr[reg].mipsReg].nReg = (int)INVALID_REG;
|
||||
nr[reg].mipsReg = IRREG_INVALID;
|
||||
nr[reg].isDirty = false;
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::FlushR(IRReg r) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
_dbg_assert_(IsValidFPR(r));
|
||||
RiscVReg reg = RiscVRegForFlush(r);
|
||||
if (reg != INVALID_REG)
|
||||
FlushRiscVReg(reg);
|
||||
FlushNativeReg((IRNativeReg)(reg - F0));
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCacheFPU::RiscVRegForFlush(IRReg r) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
switch (mr[r].loc) {
|
||||
_dbg_assert_(IsValidFPR(r));
|
||||
switch (mr[r + 32].loc) {
|
||||
case MIPSLoc::FREG:
|
||||
_assert_msg_(mr[r].nReg != INVALID_REG, "RiscVRegForFlush: IR %d had bad RiscVReg", r);
|
||||
if (mr[r].nReg == INVALID_REG) {
|
||||
_assert_msg_(mr[r + 32].nReg != INVALID_REG, "RiscVRegForFlush: IR %d had bad RiscVReg", r + 32);
|
||||
if (mr[r + 32].nReg == INVALID_REG) {
|
||||
return INVALID_REG;
|
||||
}
|
||||
return (RiscVReg)(F0 + mr[r].nReg);
|
||||
return (RiscVReg)(F0 + mr[r + 32].nReg);
|
||||
|
||||
case MIPSLoc::MEM:
|
||||
return INVALID_REG;
|
||||
@ -295,13 +219,13 @@ void RiscVRegCacheFPU::FlushBeforeCall() {
|
||||
|
||||
// These registers are not preserved by function calls.
|
||||
for (int i = 0; i <= 7; ++i) {
|
||||
FlushRiscVReg(RiscVReg(F0 + i));
|
||||
FlushNativeReg(i);
|
||||
}
|
||||
for (int i = 10; i <= 17; ++i) {
|
||||
FlushRiscVReg(RiscVReg(F0 + i));
|
||||
FlushNativeReg(i);
|
||||
}
|
||||
for (int i = 28; i <= 31; ++i) {
|
||||
FlushRiscVReg(RiscVReg(F0 + i));
|
||||
FlushNativeReg(i);
|
||||
}
|
||||
}
|
||||
|
||||
@ -311,16 +235,16 @@ void RiscVRegCacheFPU::FlushAll() {
|
||||
return;
|
||||
}
|
||||
|
||||
int numRVRegs = 0;
|
||||
const RiscVReg *order = GetMIPSAllocationOrder(numRVRegs);
|
||||
int numRVRegs = 0, baseIndex = 0;
|
||||
const int *order = GetAllocationOrder(MIPSLoc::FREG, numRVRegs, baseIndex);
|
||||
|
||||
for (int i = 0; i < numRVRegs; i++) {
|
||||
int a = order[i] - F0;
|
||||
int a = order[i] - baseIndex;
|
||||
int m = nr[a].mipsReg;
|
||||
|
||||
if (nr[a].isDirty) {
|
||||
_assert_(m != MIPS_REG_INVALID);
|
||||
emit_->FS(32, order[i], CTXREG, GetMipsRegOffset(m));
|
||||
emit_->FS(32, (RiscVReg)(F0 + a), CTXREG, GetMipsRegOffset(m));
|
||||
|
||||
mr[m].loc = MIPSLoc::MEM;
|
||||
mr[m].nReg = (int)INVALID_REG;
|
||||
@ -339,15 +263,12 @@ void RiscVRegCacheFPU::FlushAll() {
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::DiscardR(IRReg r) {
|
||||
_dbg_assert_(IsValidReg(r));
|
||||
switch (mr[r].loc) {
|
||||
_dbg_assert_(IsValidFPR(r));
|
||||
switch (mr[r + 32].loc) {
|
||||
case MIPSLoc::FREG:
|
||||
_assert_(mr[r].nReg != INVALID_REG);
|
||||
if (mr[r].nReg != INVALID_REG) {
|
||||
// Note that we DO NOT write it back here. That's the whole point of Discard.
|
||||
nr[mr[r].nReg].isDirty = false;
|
||||
nr[mr[r].nReg].mipsReg = IRREG_INVALID;
|
||||
}
|
||||
_assert_(mr[r + 32].nReg != INVALID_REG);
|
||||
// Note that we DO NOT write it back here. That's the whole point of Discard.
|
||||
DiscardNativeReg(mr[r + 32].nReg);
|
||||
break;
|
||||
|
||||
case MIPSLoc::MEM:
|
||||
@ -358,77 +279,59 @@ void RiscVRegCacheFPU::DiscardR(IRReg r) {
|
||||
_assert_(false);
|
||||
break;
|
||||
}
|
||||
mr[r].loc = MIPSLoc::MEM;
|
||||
mr[r].nReg = (int)INVALID_REG;
|
||||
mr[r].spillLockIRIndex = -1;
|
||||
mr[r + 32].loc = MIPSLoc::MEM;
|
||||
mr[r + 32].nReg = -1;
|
||||
mr[r + 32].spillLockIRIndex = -1;
|
||||
}
|
||||
|
||||
int RiscVRegCacheFPU::GetMipsRegOffset(IRReg r) {
|
||||
_assert_(IsValidReg(r));
|
||||
_assert_(IsValidFPR(r - 32));
|
||||
// These are offsets within the MIPSState structure.
|
||||
// IR gives us an index that is already 32 after the state index (skipping GPRs.)
|
||||
return (32 + r) * 4;
|
||||
return (r) * 4;
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::SpillLock(IRReg r1, IRReg r2, IRReg r3, IRReg r4) {
|
||||
_dbg_assert_(IsValidReg(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidReg(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidReg(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidReg(r4));
|
||||
mr[r1].spillLockIRIndex = irIndex_;
|
||||
_dbg_assert_(IsValidFPR(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidFPR(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidFPR(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidFPR(r4));
|
||||
mr[r1 + 32].spillLockIRIndex = irIndex_;
|
||||
if (r2 != IRREG_INVALID)
|
||||
mr[r2].spillLockIRIndex = irIndex_;
|
||||
mr[r2 + 32].spillLockIRIndex = irIndex_;
|
||||
if (r3 != IRREG_INVALID)
|
||||
mr[r3].spillLockIRIndex = irIndex_;
|
||||
mr[r3 + 32].spillLockIRIndex = irIndex_;
|
||||
if (r4 != IRREG_INVALID)
|
||||
mr[r4].spillLockIRIndex = irIndex_;
|
||||
mr[r4 + 32].spillLockIRIndex = irIndex_;
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::ReleaseSpillLock(IRReg r1, IRReg r2, IRReg r3, IRReg r4) {
|
||||
_dbg_assert_(IsValidReg(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidReg(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidReg(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidReg(r4));
|
||||
mr[r1].spillLockIRIndex = -1;
|
||||
_dbg_assert_(IsValidFPR(r1));
|
||||
_dbg_assert_(r2 == IRREG_INVALID || IsValidFPR(r2));
|
||||
_dbg_assert_(r3 == IRREG_INVALID || IsValidFPR(r3));
|
||||
_dbg_assert_(r4 == IRREG_INVALID || IsValidFPR(r4));
|
||||
mr[r1 + 32].spillLockIRIndex = -1;
|
||||
if (r2 != IRREG_INVALID)
|
||||
mr[r2].spillLockIRIndex = -1;
|
||||
mr[r2 + 32].spillLockIRIndex = -1;
|
||||
if (r3 != IRREG_INVALID)
|
||||
mr[r3].spillLockIRIndex = -1;
|
||||
mr[r3 + 32].spillLockIRIndex = -1;
|
||||
if (r4 != IRREG_INVALID)
|
||||
mr[r4].spillLockIRIndex = -1;
|
||||
mr[r4 + 32].spillLockIRIndex = -1;
|
||||
}
|
||||
|
||||
RiscVReg RiscVRegCacheFPU::R(IRReg mipsReg) {
|
||||
_dbg_assert_(IsValidReg(mipsReg));
|
||||
_dbg_assert_(mr[mipsReg].loc == MIPSLoc::FREG);
|
||||
if (mr[mipsReg].loc == MIPSLoc::FREG) {
|
||||
return (RiscVReg)(mr[mipsReg].nReg + F0);
|
||||
_dbg_assert_(IsValidFPR(mipsReg));
|
||||
_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::FREG);
|
||||
if (mr[mipsReg + 32].loc == MIPSLoc::FREG) {
|
||||
return (RiscVReg)(mr[mipsReg + 32].nReg + F0);
|
||||
} else {
|
||||
ERROR_LOG_REPORT(JIT, "Reg %i not in riscv reg", mipsReg);
|
||||
return INVALID_REG; // BAAAD
|
||||
}
|
||||
}
|
||||
|
||||
bool RiscVRegCacheFPU::IsValidReg(IRReg r) const {
|
||||
if (r < 0 || r >= NUM_MIPSFPUREG)
|
||||
return false;
|
||||
|
||||
// See MIPSState for these offsets.
|
||||
int index = r + 32;
|
||||
|
||||
// Allow FPU or VFPU regs here.
|
||||
if (index >= 32 && index < 32 + 32 + 128)
|
||||
return true;
|
||||
// Also allow VFPU temps.
|
||||
if (index >= 224 && index < 224 + 16)
|
||||
return true;
|
||||
|
||||
// Nothing else is allowed for the FPU side cache.
|
||||
return false;
|
||||
}
|
||||
|
||||
void RiscVRegCacheFPU::SetupInitialRegs() {
|
||||
IRNativeRegCache::SetupInitialRegs();
|
||||
IRNativeRegCacheBase::SetupInitialRegs();
|
||||
|
||||
// TODO: Move to a shared cache?
|
||||
mrInitial_[0].loc = MIPSLoc::MEM;
|
||||
|
||||
@ -25,7 +25,7 @@ namespace MIPSComp {
|
||||
struct JitOptions;
|
||||
}
|
||||
|
||||
class RiscVRegCacheFPU : public IRNativeRegCache {
|
||||
class RiscVRegCacheFPU : public IRNativeRegCacheBase {
|
||||
public:
|
||||
RiscVRegCacheFPU(MIPSComp::JitOptions *jo);
|
||||
|
||||
@ -52,23 +52,19 @@ public:
|
||||
void FlushBeforeCall();
|
||||
void FlushAll();
|
||||
void FlushR(IRReg r);
|
||||
void FlushRiscVReg(RiscVGen::RiscVReg r);
|
||||
void DiscardR(IRReg r);
|
||||
|
||||
RiscVGen::RiscVReg R(IRReg preg); // Returns a cached register
|
||||
|
||||
protected:
|
||||
void SetupInitialRegs() override;
|
||||
const int *GetAllocationOrder(MIPSLoc type, int &count, int &base) const override;
|
||||
void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
|
||||
|
||||
private:
|
||||
const RiscVGen::RiscVReg *GetMIPSAllocationOrder(int &count);
|
||||
RiscVGen::RiscVReg AllocateReg();
|
||||
RiscVGen::RiscVReg FindBestToSpill(bool unusedOnly, bool *clobbered);
|
||||
RiscVGen::RiscVReg RiscVRegForFlush(IRReg r);
|
||||
int GetMipsRegOffset(IRReg r);
|
||||
|
||||
bool IsValidReg(IRReg r) const;
|
||||
|
||||
RiscVGen::RiscVEmitter *emit_ = nullptr;
|
||||
|
||||
enum {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user