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Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm
This commit is contained in:
Henrik Rydgard
parent
0698515274
commit
f544364c4a
@ -1363,7 +1363,7 @@ namespace MIPSComp {
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bool unsignedOp = ((op >> 16) & 1) == 0; // vi2uc (0), vi2us (2)
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// These instructions pack pairs or quads of integers into 32 bits.
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// The unsigned (u) versions skip the sign bit when packing, but first clamping to 0.
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// The unsigned (u) versions skip the sign bit when packing, first doing a signed clamp to 0 (so the sign bit won't ever be 1).
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VectorSize sz = GetVecSize(op);
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VectorSize outsize;
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@ -1422,7 +1422,6 @@ namespace MIPSComp {
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ir.Write(IROp::Vec2Pack31To16, tempregs[1], IRVTEMP_0 + 2);
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}
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} else { //vi2s
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DISABLE; // Can't figure out what's wrong with this! Doesn't pass cpu/vfpu/convert
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ir.Write(IROp::Vec2Pack32To16, tempregs[0], srcregs[0]);
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if (outsize == V_Pair) {
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ir.Write(IROp::Vec2Pack32To16, tempregs[1], srcregs[2]);
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@ -1459,6 +1458,7 @@ namespace MIPSComp {
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VectorSize outsize;
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if (bits == 8) {
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outsize = V_Quad;
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sz = V_Single; // For some reason, sz is set to Quad in this case though the outsize is Single.
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} else {
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switch (sz) {
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case V_Single:
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@ -3,6 +3,18 @@
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#include "Core/MIPS/IR/IRPassSimplify.h"
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#include "Core/MIPS/MIPSDebugInterface.h"
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// Legend
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// ======================
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// _ = ignore
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// G = GPR register
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// C = 32-bit constant from array
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// I = immediate value from instruction
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// F = FPR register, single
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// V = FPR register, Vec4. Reg number always divisible by 4.
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// 2 = FPR register, Vec2 (uncommon)
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// v = Vec4Init constant, chosen by immediate
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// s = Shuffle immediate (4 2-bit fields, choosing a xyzw shuffle)
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static const IRMeta irMeta[] = {
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{ IROp::Nop, "Nop", "" },
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{ IROp::SetConst, "SetConst", "GC" },
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@ -60,12 +72,12 @@ static const IRMeta irMeta[] = {
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{ IROp::Load16Ext, "Load16Ext", "GGC" },
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{ IROp::Load32, "Load32", "GGC" },
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{ IROp::LoadFloat, "LoadFloat", "FGC" },
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{ IROp::LoadVec4, "LoadVec4", "FGC" },
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{ IROp::LoadVec4, "LoadVec4", "VGC" },
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{ IROp::Store8, "Store8", "GGC", IRFLAG_SRC3 },
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{ IROp::Store16, "Store16", "GGC", IRFLAG_SRC3 },
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{ IROp::Store32, "Store32", "GGC", IRFLAG_SRC3 },
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{ IROp::StoreFloat, "StoreFloat", "FGC", IRFLAG_SRC3 },
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{ IROp::StoreVec4, "StoreVec4", "FGC", IRFLAG_SRC3 },
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{ IROp::StoreVec4, "StoreVec4", "VGC", IRFLAG_SRC3 },
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{ IROp::FAdd, "FAdd", "FFF" },
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{ IROp::FSub, "FSub", "FFF" },
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{ IROp::FMul, "FMul", "FFF" },
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@ -103,30 +115,30 @@ static const IRMeta irMeta[] = {
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{ IROp::FCmovVfpuCC, "FCmovVfpuCC", "FFI" },
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{ IROp::FCmpVfpuBit, "FCmpVfpuBit", "IFF" },
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{ IROp::FCmpVfpuAggregate, "FCmpVfpuAggregate", "" },
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{ IROp::Vec4Init, "Vec4Init", "Fv" },
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{ IROp::Vec4Shuffle, "Vec4Shuffle", "FFs" },
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{ IROp::Vec4Mov, "Vec4Mov", "FF" },
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{ IROp::Vec4Add, "Vec4Add", "FFF" },
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{ IROp::Vec4Sub, "Vec4Sub", "FFF" },
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{ IROp::Vec4Div, "Vec4Div", "FFF" },
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{ IROp::Vec4Mul, "Vec4Mul", "FFF" },
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{ IROp::Vec4Scale, "Vec4Scale", "FFF" },
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{ IROp::Vec4Dot, "Vec4Dot", "FFF" },
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{ IROp::Vec4Neg, "Vec4Neg", "FF" },
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{ IROp::Vec4Abs, "Vec4Abs", "FF" },
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{ IROp::Vec4Init, "Vec4Init", "Vv" },
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{ IROp::Vec4Shuffle, "Vec4Shuffle", "VVs" },
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{ IROp::Vec4Mov, "Vec4Mov", "VV" },
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{ IROp::Vec4Add, "Vec4Add", "VVV" },
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{ IROp::Vec4Sub, "Vec4Sub", "VVV" },
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{ IROp::Vec4Div, "Vec4Div", "VVV" },
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{ IROp::Vec4Mul, "Vec4Mul", "VVV" },
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{ IROp::Vec4Scale, "Vec4Scale", "VVF" },
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{ IROp::Vec4Dot, "Vec4Dot", "FVV" },
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{ IROp::Vec4Neg, "Vec4Neg", "VV" },
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{ IROp::Vec4Abs, "Vec4Abs", "VV" },
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// Pack/Unpack
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{ IROp::Vec2Unpack16To31, "Vec2Unpack16To31", "FF" }, // Note that the result is shifted down by 1, hence 31
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{ IROp::Vec2Unpack16To32, "Vec2Unpack16To32", "FF" },
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{ IROp::Vec4Unpack8To32, "Vec4Unpack8To32", "FF" },
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{ IROp::Vec4DuplicateUpperBitsAndShift1, "Vec4DuplicateUpperBitsAndShift1", "FF" },
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{ IROp::Vec2Unpack16To31, "Vec2Unpack16To31", "2F" }, // Note that the result is shifted down by 1, hence 31
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{ IROp::Vec2Unpack16To32, "Vec2Unpack16To32", "2F" },
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{ IROp::Vec4Unpack8To32, "Vec4Unpack8To32", "VF" },
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{ IROp::Vec4DuplicateUpperBitsAndShift1, "Vec4DuplicateUpperBitsAndShift1", "VV" },
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{ IROp::Vec4ClampToZero, "Vec4ClampToZero", "FF" },
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{ IROp::Vec2ClampToZero, "Vec2ClampToZero", "FF" },
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{ IROp::Vec4Pack32To8, "Vec4Pack32To8", "FF" },
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{ IROp::Vec4Pack31To8, "Vec4Pack31To8", "FF" },
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{ IROp::Vec2Pack32To16, "Vec2Pack32To16", "FF" },
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{ IROp::Vec2Pack31To16, "Vec2Pack31To16", "FF" },
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{ IROp::Vec4ClampToZero, "Vec4ClampToZero", "VV" },
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{ IROp::Vec2ClampToZero, "Vec2ClampToZero", "22" },
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{ IROp::Vec4Pack32To8, "Vec4Pack32To8", "FV" },
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{ IROp::Vec4Pack31To8, "Vec4Pack31To8", "FV" },
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{ IROp::Vec2Pack32To16, "Vec2Pack32To16", "2V" },
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{ IROp::Vec2Pack31To16, "Vec2Pack31To16", "2V" },
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{ IROp::Interpret, "Interpret", "_C" },
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{ IROp::Downcount, "Downcount", "_II" },
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@ -240,6 +252,20 @@ void DisassembleParam(char *buf, int bufSize, u8 param, char type, const u32 *co
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snprintf(buf, bufSize, "f%d", param);
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}
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break;
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case 'V':
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if (param >= 32) {
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snprintf(buf, bufSize, "v%d..v%d", param - 32, param - 32 + 3);
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} else {
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snprintf(buf, bufSize, "f%d..f%d", param, param + 3);
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}
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break;
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case '2':
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if (param >= 32) {
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snprintf(buf, bufSize, "v%d,v%d", param - 32, param - 32 + 1);
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} else {
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snprintf(buf, bufSize, "f%d,f%d", param, param + 1);
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}
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break;
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case 'C':
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snprintf(buf, bufSize, "%08x", constPool[param]);
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break;
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@ -246,7 +246,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
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case IROp::Vec2Pack32To16:
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{
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u32 val = mips->fi[inst->src1] >> 16;
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mips->fi[inst->dest] = (mips->fi[inst->src1 + 1] & 0xFFFF) | val;
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mips->fi[inst->dest] = (mips->fi[inst->src1 + 1] & 0xFFFF0000) | val;
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break;
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}
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@ -202,6 +202,19 @@ bool ThreeOpToTwoOp(const IRWriter &in, IRWriter &out) {
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out.Write(inst);
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}
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break;
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case IROp::Vec4Add:
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case IROp::Vec4Sub:
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case IROp::Vec4Mul:
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case IROp::Vec4Div:
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if (inst.src1 != inst.dest && inst.src2 != inst.dest) {
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out.Write(IROp::Vec4Mov, inst.dest, inst.src1);
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out.Write(inst.op, inst.dest, inst.dest, inst.src2);
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} else {
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out.Write(inst);
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}
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break;
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default:
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out.Write(inst);
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break;
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@ -1801,7 +1801,8 @@ void Jit::Comp_Vf2i(MIPSOpcode op) {
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const double *mult = &mulTableVf2i[imm];
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int setMXCSR = -1;
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switch ((op >> 21) & 0x1f) {
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int rmode = (op >> 21) & 0x1f;
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switch (rmode) {
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case 17:
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break; //z - truncate. Easy to support.
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case 16:
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