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interp: Centralize memory size handling.

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Unknown W. Brackets 2022-11-13 17:38:53 -08:00
parent 76cf4dbf12
commit f9da9e6b60
6 changed files with 26 additions and 53 deletions
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18
Core/Debugger/DisassemblyManager.cpp
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@ -709,22 +709,8 @@ void DisassemblyFunction::load()
case 0x2B: // sw
macro = new DisassemblyMacro(opAddress);
int dataSize;
switch (nextInfo & MEMTYPE_MASK) {
case MEMTYPE_BYTE:
dataSize = 1;
break;
case MEMTYPE_HWORD:
dataSize = 2;
break;
case MEMTYPE_WORD:
case MEMTYPE_FLOAT:
dataSize = 4;
break;
case MEMTYPE_VQUAD:
dataSize = 16;
break;
default:
int dataSize = MIPSGetMemoryAccessSize(next);
if (dataSize == 0) {
delete macro;
return;
}

36
Core/MIPS/MIPSAnalyst.cpp
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@ -611,25 +611,7 @@ namespace MIPSAnalyst {
int OpMemoryAccessSize(u32 pc) {
const auto op = Memory::Read_Instruction(pc, true);
MIPSInfo info = MIPSGetInfo(op);
if ((info & (IN_MEM | OUT_MEM)) == 0) {
return 0;
}
// TODO: Verify lwl/lwr/etc.?
switch (info & MEMTYPE_MASK) {
case MEMTYPE_BYTE:
return 1;
case MEMTYPE_HWORD:
return 2;
case MEMTYPE_WORD:
case MEMTYPE_FLOAT:
return 4;
case MEMTYPE_VQUAD:
return 16;
}
return 0;
return MIPSGetMemoryAccessSize(op);
}
bool IsOpMemoryWrite(u32 pc) {
@ -1553,21 +1535,7 @@ skip:
// lw, sh, ...
if (!IsSyscall(op) && (opInfo & (IN_MEM | OUT_MEM)) != 0) {
info.isDataAccess = true;
switch (opInfo & MEMTYPE_MASK) {
case MEMTYPE_BYTE:
info.dataSize = 1;
break;
case MEMTYPE_HWORD:
info.dataSize = 2;
break;
case MEMTYPE_WORD:
case MEMTYPE_FLOAT:
info.dataSize = 4;
break;
case MEMTYPE_VQUAD:
info.dataSize = 16;
}
info.dataSize = MIPSGetMemoryAccessSize(op);
u32 rs = cpu->GetRegValue(0, (int)MIPS_GET_RS(op));
s16 imm16 = op & 0xFFFF;

2
Core/MIPS/MIPSInt.h
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@ -23,8 +23,6 @@ int MIPS_SingleStep();
namespace MIPSInt
{
void Int_Unknown(MIPSOpcode op);
void Int_Unimpl(MIPSOpcode op);
void Int_Syscall(MIPSOpcode op);
void Int_mxc1(MIPSOpcode op);

1
Core/MIPS/MIPSIntVFPU.h
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@ -26,7 +26,6 @@ namespace MIPSInt
void Int_SV(MIPSOpcode op);
void Int_SVQ(MIPSOpcode op);
void Int_Mftv(MIPSOpcode op);
void Int_MatrixSet(MIPSOpcode op);
void Int_VecDo3(MIPSOpcode op);
void Int_Vcst(MIPSOpcode op);
void Int_VMatrixInit(MIPSOpcode op);

21
Core/MIPS/MIPSTables.cpp
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@ -1081,6 +1081,27 @@ int MIPSGetInstructionCycleEstimate(MIPSOpcode op)
return GetInstructionCycleEstimate(instr);
}
int MIPSGetMemoryAccessSize(MIPSOpcode op) {
MIPSInfo info = MIPSGetInfo(op);
if ((info & (IN_MEM | OUT_MEM)) == 0) {
return 0;
}
switch (info & MEMTYPE_MASK) {
case MEMTYPE_BYTE:
return 1;
case MEMTYPE_HWORD:
return 2;
case MEMTYPE_WORD:
case MEMTYPE_FLOAT:
return 4;
case MEMTYPE_VQUAD:
return 16;
}
return 0;
}
const char *MIPSDisasmAt(u32 compilerPC) {
static char temp[256];
MIPSDisAsm(Memory::Read_Instruction(compilerPC), 0, temp);

1
Core/MIPS/MIPSTables.h
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@ -130,5 +130,6 @@ int MIPSInterpret_RunUntil(u64 globalTicks);
MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op);
int MIPSGetInstructionCycleEstimate(MIPSOpcode op);
int MIPSGetMemoryAccessSize(MIPSOpcode op);
const char *MIPSGetName(MIPSOpcode op);
const char *MIPSDisasmAt(u32 compilerPC);