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ARM32: Remove runtime checks for VFPv3 and NEON since we require these when building anyway.

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This commit is contained in:
Henrik Rydgård 2024-07-17 22:13:22 +02:00
parent 320a1cfc8f
commit fb499bf5bf
2 changed files with 3 additions and 112 deletions
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113
Common/ArmEmitter.cpp
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@ -166,7 +166,7 @@ void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg, bool negate)
conv.f = negate ? -val : val;
// Try moving directly first if mantisse is empty
Operand2 op2;
if (cpu_info.bVFPv3 && TryMakeFloatIMM8(conv.u, op2))
if (TryMakeFloatIMM8(conv.u, op2))
VMOV(dest, op2);
else
{
@ -182,7 +182,7 @@ void ARMXEmitter::MOVI2F_neon(ARMReg dest, float val, ARMReg tempReg, bool negat
conv.f = negate ? -val : val;
// Try moving directly first if mantisse is empty
Operand2 op2;
if (cpu_info.bVFPv3 && TryMakeFloatIMM8(conv.u, op2))
if (TryMakeFloatIMM8(conv.u, op2))
VMOV_neon(F_32, dest, conv.u);
else
{
@ -1264,7 +1264,6 @@ void ARMXEmitter::LDMBitmask(ARMReg dest, bool Add, bool Before, bool WriteBack,
void ARMXEmitter::VABD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_assert_msg_(Vd >= D0, "Pass invalid register to VABD(float)");
_assert_msg_(cpu_info.bNEON, "Can't use VABD(float) when CPU doesn't support it");
bool register_quad = Vd >= Q0;
// Gets encoded as a double register
@ -1279,7 +1278,6 @@ void ARMXEmitter::VABD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_assert_msg_(Vd >= D0, "Pass invalid register to VADD(integer)");
_assert_msg_(cpu_info.bNEON, "Can't use VADD(integer) when CPU doesn't support it");
bool register_quad = Vd >= Q0;
@ -1296,7 +1294,6 @@ void ARMXEmitter::VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_assert_msg_(Vd >= Q0, "Pass invalid register to VSUB(integer)");
_assert_msg_(cpu_info.bNEON, "Can't use VSUB(integer) when CPU doesn't support it");
// Gets encoded as a double register
Vd = SubBase(Vd);
@ -1564,14 +1561,12 @@ void ARMXEmitter::VMSR(ARMReg Rt) {
void ARMXEmitter::VMOV(ARMReg Dest, Operand2 op2)
{
_assert_msg_(cpu_info.bVFPv3, "VMOV #imm requires VFPv3");
int sz = Dest >= D0 ? (1 << 8) : 0;
Write32(condition | (0xEB << 20) | EncodeVd(Dest) | (5 << 9) | sz | op2.Imm8VFP());
}
void ARMXEmitter::VMOV_neon(u32 Size, ARMReg Vd, u32 imm)
{
_assert_msg_(cpu_info.bNEON, "VMOV_neon #imm requires NEON");
_assert_msg_(Vd >= D0, "VMOV_neon #imm must target a double or quad");
bool register_quad = Vd >= Q0;
@ -1656,8 +1651,6 @@ void ARMXEmitter::VMOV_neon(u32 Size, ARMReg Vd, u32 imm)
void ARMXEmitter::VMOV_neon(u32 Size, ARMReg Vd, ARMReg Rt, int lane)
{
_assert_msg_(cpu_info.bNEON, "VMOV_neon requires NEON");
int opc1 = 0;
int opc2 = 0;
@ -1697,8 +1690,6 @@ void ARMXEmitter::VMOV_neon(u32 Size, ARMReg Vd, ARMReg Rt, int lane)
void ARMXEmitter::VMOV(ARMReg Vd, ARMReg Rt, ARMReg Rt2)
{
_assert_msg_(cpu_info.bVFP || cpu_info.bNEON, "VMOV_neon requires VFP or NEON");
if (Vd < S0 && Rt < S0 && Rt2 >= D0)
{
// Oh, reading to regs, our params are backwards.
@ -1803,7 +1794,6 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
// Double and quad
if (Quad)
{
_assert_msg_(cpu_info.bNEON, "Trying to use quad registers when you don't support ASIMD.");
// Gets encoded as a Double register
Write32((0xF2 << 24) | ((Dest & 0x10) << 18) | (2 << 20) | ((Src & 0xF) << 16) \
| ((Dest & 0xF) << 12) | (1 << 8) | ((Src & 0x10) << 3) | (1 << 6) \
@ -1865,7 +1855,6 @@ void ARMXEmitter::VCVT(ARMReg Dest, ARMReg Source, int flags)
void ARMXEmitter::VABA(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -1878,7 +1867,6 @@ void ARMXEmitter::VABAL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= D0 && Vn < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | ((Size & I_UNSIGNED ? 1 : 0) << 24) | (1 << 23) | EncodeVn(Vn) \
@ -1888,7 +1876,6 @@ void ARMXEmitter::VABAL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VABD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
if (Size & F_32)
@ -1903,7 +1890,6 @@ void ARMXEmitter::VABDL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= D0 && Vn < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | ((Size & I_UNSIGNED ? 1 : 0) << 24) | (1 << 23) | EncodeVn(Vn) \
@ -1913,7 +1899,6 @@ void ARMXEmitter::VABDL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VABS(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (0xB1 << 16) | (encodedSize(Size) << 18) | EncodeVd(Vd) \
@ -1924,7 +1909,6 @@ void ARMXEmitter::VACGE(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
// Only Float
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | EncodeVn(Vn) | EncodeVd(Vd) \
@ -1935,7 +1919,6 @@ void ARMXEmitter::VACGT(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
// Only Float
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (1 << 21) | EncodeVn(Vn) | EncodeVd(Vd) \
@ -1955,7 +1938,6 @@ void ARMXEmitter::VACLT(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -1971,7 +1953,6 @@ void ARMXEmitter::VADDHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) \
@ -1983,7 +1964,6 @@ void ARMXEmitter::VADDL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= D0 && Vn < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | ((Size & I_UNSIGNED ? 1 : 0) << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) \
@ -1994,7 +1974,6 @@ void ARMXEmitter::VADDW(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | ((Size & I_UNSIGNED ? 1 : 0) << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) \
@ -2003,7 +1982,6 @@ void ARMXEmitter::VADDW(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VAND(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Vd == Vn && Vn == Vm), "All operands the same for %s is a nop", __FUNCTION__);
// _dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2013,7 +1991,6 @@ void ARMXEmitter::VAND(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VBIC(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// _dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2022,7 +1999,6 @@ void ARMXEmitter::VBIC(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VEOR(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s: %i", __FUNCTION__, Vd);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | EncodeVn(Vn) | EncodeVd(Vd) | (0x11 << 4) | (register_quad << 6) | EncodeVm(Vm));
@ -2030,7 +2006,6 @@ void ARMXEmitter::VEOR(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VBIF(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// _dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2039,7 +2014,6 @@ void ARMXEmitter::VBIF(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VBIT(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// _dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2048,7 +2022,6 @@ void ARMXEmitter::VBIT(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VBSL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// _dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2057,7 +2030,6 @@ void ARMXEmitter::VBSL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VCEQ(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
if (Size & F_32)
@ -2070,7 +2042,6 @@ void ARMXEmitter::VCEQ(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VCEQ(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2080,7 +2051,6 @@ void ARMXEmitter::VCEQ(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VCGE(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
if (Size & F_32)
@ -2092,7 +2062,6 @@ void ARMXEmitter::VCGE(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VCGE(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (0xB << 20) | (encodedSize(Size) << 18) | (1 << 16) \
@ -2101,7 +2070,6 @@ void ARMXEmitter::VCGE(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VCGT(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
if (Size & F_32)
@ -2113,7 +2081,6 @@ void ARMXEmitter::VCGT(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VCGT(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (0xD << 20) | (encodedSize(Size) << 18) | (1 << 16) \
@ -2126,7 +2093,6 @@ void ARMXEmitter::VCLE(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VCLE(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (0xD << 20) | (encodedSize(Size) << 18) | (1 << 16) \
@ -2135,7 +2101,6 @@ void ARMXEmitter::VCLE(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VCLS(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2149,7 +2114,6 @@ void ARMXEmitter::VCLT(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VCLT(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (0xD << 20) | (encodedSize(Size) << 18) | (1 << 16) \
@ -2158,7 +2122,6 @@ void ARMXEmitter::VCLT(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VCLZ(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF3 << 24) | (0xD << 20) | (encodedSize(Size) << 18) \
@ -2167,7 +2130,6 @@ void ARMXEmitter::VCLZ(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VCNT(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(Size & I_8, "Can only use I_8 with %s", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2178,7 +2140,6 @@ void ARMXEmitter::VDUP(u32 Size, ARMReg Vd, ARMReg Vm, u8 index)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
u32 imm4 = 0;
@ -2195,7 +2156,6 @@ void ARMXEmitter::VDUP(u32 Size, ARMReg Vd, ARMReg Rt)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Rt < S0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Vd = SubBase(Vd);
@ -2213,7 +2173,6 @@ void ARMXEmitter::VDUP(u32 Size, ARMReg Vd, ARMReg Rt)
void ARMXEmitter::VEXT(ARMReg Vd, ARMReg Vn, ARMReg Vm, u8 index)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Write32((0xF2 << 24) | (0xB << 20) | EncodeVn(Vn) | EncodeVd(Vd) | (index & 0xF) \
@ -2223,7 +2182,6 @@ void ARMXEmitter::VFMA(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Size == F_32, "Passed invalid size to FP-only NEON instruction");
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bVFPv4, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2233,7 +2191,6 @@ void ARMXEmitter::VFMS(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Size == F_32, "Passed invalid size to FP-only NEON instruction");
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bVFPv4, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2242,7 +2199,6 @@ void ARMXEmitter::VFMS(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VHADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2253,7 +2209,6 @@ void ARMXEmitter::VHADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VHSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2264,7 +2219,6 @@ void ARMXEmitter::VHSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMAX(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2277,7 +2231,6 @@ void ARMXEmitter::VMAX(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMIN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2290,7 +2243,6 @@ void ARMXEmitter::VMIN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMLA(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2302,7 +2254,6 @@ void ARMXEmitter::VMLA(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMLS(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2316,7 +2267,6 @@ void ARMXEmitter::VMLAL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | ((Size & I_UNSIGNED ? 1 : 0) << 24) | (encodedSize(Size) << 20) \
@ -2327,7 +2277,6 @@ void ARMXEmitter::VMLSL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vn >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm < Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float.", __FUNCTION__);
Write32((0xF2 << 24) | ((Size & I_UNSIGNED ? 1 : 0) << 24) | (encodedSize(Size) << 20) \
@ -2336,7 +2285,6 @@ void ARMXEmitter::VMLSL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMUL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2349,7 +2297,6 @@ void ARMXEmitter::VMUL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMULL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF2 << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2358,7 +2305,6 @@ void ARMXEmitter::VMULL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMLA_scalar(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2374,7 +2320,6 @@ void ARMXEmitter::VMLA_scalar(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMUL_scalar(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2393,7 +2338,6 @@ void ARMXEmitter::VMUL_scalar(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VMVN(ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2404,7 +2348,6 @@ void ARMXEmitter::VMVN(ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VNEG(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2414,7 +2357,6 @@ void ARMXEmitter::VNEG(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VORN(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2423,7 +2365,6 @@ void ARMXEmitter::VORN(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VORR(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Vd == Vn && Vn == Vm), "All operands the same for %s is a nop", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2433,7 +2374,6 @@ void ARMXEmitter::VORR(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VPADAL(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2444,7 +2384,6 @@ void ARMXEmitter::VPADAL(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VPADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
if (Size & F_32)
Write32((0xF3 << 24) | EncodeVn(Vn) | EncodeVd(Vd) | (0xD0 << 4) | EncodeVm(Vm));
@ -2455,7 +2394,6 @@ void ARMXEmitter::VPADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VPADDL(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2466,7 +2404,6 @@ void ARMXEmitter::VPADDL(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VPMAX(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
if (Size & F_32)
Write32((0xF3 << 24) | EncodeVn(Vn) | EncodeVd(Vd) | (0xF0 << 4) | EncodeVm(Vm));
@ -2477,7 +2414,6 @@ void ARMXEmitter::VPMAX(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VPMIN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
if (Size & F_32)
Write32((0xF3 << 24) | (1 << 21) | EncodeVn(Vn) | EncodeVd(Vd) | (0xF0 << 4) | EncodeVm(Vm));
@ -2488,7 +2424,6 @@ void ARMXEmitter::VPMIN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQABS(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2499,7 +2434,6 @@ void ARMXEmitter::VQABS(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VQADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2510,7 +2444,6 @@ void ARMXEmitter::VQADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQDMLAL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF2 << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2519,7 +2452,6 @@ void ARMXEmitter::VQDMLAL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQDMLSL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF2 << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2528,7 +2460,6 @@ void ARMXEmitter::VQDMLSL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQDMULH(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF2 << 24) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2537,7 +2468,6 @@ void ARMXEmitter::VQDMULH(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQDMULL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF2 << 24) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2546,7 +2476,6 @@ void ARMXEmitter::VQDMULL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQNEG(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2557,7 +2486,6 @@ void ARMXEmitter::VQNEG(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VQRDMULH(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF3 << 24) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2566,7 +2494,6 @@ void ARMXEmitter::VQRDMULH(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQRSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2577,7 +2504,6 @@ void ARMXEmitter::VQRSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2588,7 +2514,6 @@ void ARMXEmitter::VQSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VQSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2599,7 +2524,6 @@ void ARMXEmitter::VQSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VRADDHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF3 << 24) | (1 << 23) | ((encodedSize(Size) - 1) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2608,7 +2532,6 @@ void ARMXEmitter::VRADDHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VRECPE(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2618,7 +2541,6 @@ void ARMXEmitter::VRECPE(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VRECPS(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2627,7 +2549,6 @@ void ARMXEmitter::VRECPS(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VRHADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2638,7 +2559,6 @@ void ARMXEmitter::VRHADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VRSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2649,7 +2569,6 @@ void ARMXEmitter::VRSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VRSQRTE(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
Vd = SubBase(Vd);
@ -2662,7 +2581,6 @@ void ARMXEmitter::VRSQRTE(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VRSQRTS(ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2672,7 +2590,6 @@ void ARMXEmitter::VRSQRTS(ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VRSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
Write32((0xF3 << 24) | (1 << 23) | ((encodedSize(Size) - 1) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
@ -2681,7 +2598,6 @@ void ARMXEmitter::VRSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VSHL(u32 Size, ARMReg Vd, ARMReg Vm, ARMReg Vn)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2710,7 +2626,6 @@ static int EncodeSizeShift(u32 Size, int amount, bool inverse, bool halve) {
void ARMXEmitter::EncodeShiftByImm(u32 Size, ARMReg Vd, ARMReg Vm, int shiftAmount, u8 opcode, bool register_quad, bool inverse, bool halve) {
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_(!(Size & F_32), "%s doesn't support float", __FUNCTION__);
int imm7 = EncodeSizeShift(Size, shiftAmount, inverse, halve);
int L = (imm7 >> 6) & 1;
@ -2754,7 +2669,6 @@ void ARMXEmitter::VSHRN(u32 Size, ARMReg Vd, ARMReg Vm, int shiftAmount) {
void ARMXEmitter::VSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2768,7 +2682,6 @@ void ARMXEmitter::VSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
Write32((0xF2 << 24) | (1 << 23) | ((encodedSize(Size) - 1) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
(0x60 << 4) | EncodeVm(Vm));
@ -2776,7 +2689,6 @@ void ARMXEmitter::VSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VSUBL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
Write32((0xF2 << 24) | (Size & I_UNSIGNED ? 1 << 24 : 0) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
(0x20 << 4) | EncodeVm(Vm));
@ -2784,7 +2696,6 @@ void ARMXEmitter::VSUBL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VSUBW(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
Write32((0xF2 << 24) | (Size & I_UNSIGNED ? 1 << 24 : 0) | (1 << 23) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
(0x30 << 4) | EncodeVm(Vm));
@ -2792,7 +2703,6 @@ void ARMXEmitter::VSUBW(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VSWP(ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2802,7 +2712,6 @@ void ARMXEmitter::VSWP(ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VTRN(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2812,7 +2721,6 @@ void ARMXEmitter::VTRN(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VTST(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2822,7 +2730,6 @@ void ARMXEmitter::VTST(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
void ARMXEmitter::VUZP(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2832,7 +2739,6 @@ void ARMXEmitter::VUZP(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VZIP(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= D0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
bool register_quad = Vd >= Q0;
@ -2844,7 +2750,6 @@ void ARMXEmitter::VMOVL(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vd >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vm >= D0 && Vm <= D31, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_((Size & (I_UNSIGNED | I_SIGNED)) != 0, "Must specify I_SIGNED or I_UNSIGNED in VMOVL");
bool unsign = (Size & I_UNSIGNED) != 0;
@ -2861,7 +2766,6 @@ void ARMXEmitter::VMOVN(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vm >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vd >= D0 && Vd <= D31, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_((Size & I_8) == 0, "%s cannot narrow from I_8", __FUNCTION__);
// For consistency with assembler syntax and VMOVL - encode one size down.
@ -2874,7 +2778,6 @@ void ARMXEmitter::VQMOVN(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vm >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vd >= D0 && Vd <= D31, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_((Size & (I_UNSIGNED | I_SIGNED)) != 0, "Must specify I_SIGNED or I_UNSIGNED in %s NEON", __FUNCTION__);
_dbg_assert_msg_((Size & I_8) == 0, "%s cannot narrow from I_8", __FUNCTION__);
@ -2888,7 +2791,6 @@ void ARMXEmitter::VQMOVUN(u32 Size, ARMReg Vd, ARMReg Vm)
{
_dbg_assert_msg_(Vm >= Q0, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(Vd >= D0 && Vd <= D31, "Pass invalid register to %s", __FUNCTION__);
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
_dbg_assert_msg_((Size & I_8) == 0, "%s cannot narrow from I_8", __FUNCTION__);
u32 halfSize = encodedSize(Size) - 1;
@ -2940,12 +2842,10 @@ void ARMXEmitter::WriteVLDST1(bool load, u32 Size, ARMReg Vd, ARMReg Rn, int reg
}
void ARMXEmitter::VLD1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
WriteVLDST1(true, Size, Vd, Rn, regCount, align, Rm);
}
void ARMXEmitter::VST1(u32 Size, ARMReg Vd, ARMReg Rn, int regCount, NEONAlignment align, ARMReg Rm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
WriteVLDST1(false, Size, Vd, Rn, regCount, align, Rm);
}
@ -2975,12 +2875,10 @@ void ARMXEmitter::WriteVLDST1_lane(bool load, u32 Size, ARMReg Vd, ARMReg Rn, in
}
void ARMXEmitter::VLD1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
WriteVLDST1_lane(true, Size, Vd, Rn, lane, aligned, Rm);
}
void ARMXEmitter::VST1_lane(u32 Size, ARMReg Vd, ARMReg Rn, int lane, bool aligned, ARMReg Rm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
WriteVLDST1_lane(false, Size, Vd, Rn, lane, aligned, Rm);
}
@ -3017,7 +2915,6 @@ void ARMXEmitter::WriteVimm(ARMReg Vd, int cmode, u8 imm, int op) {
}
void ARMXEmitter::VMOV_imm(u32 Size, ARMReg Vd, VIMMMode type, int imm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// Only let through the modes that apply.
switch (type) {
case VIMM___x___x:
@ -3054,7 +2951,6 @@ error:
}
void ARMXEmitter::VMOV_immf(ARMReg Vd, float value) { // This only works with a select few values. I've hardcoded 1.0f.
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
u8 bits = 0;
if (value == 0.0f) {
@ -3076,7 +2972,6 @@ void ARMXEmitter::VMOV_immf(ARMReg Vd, float value) { // This only works with a
}
void ARMXEmitter::VORR_imm(u32 Size, ARMReg Vd, VIMMMode type, int imm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// Only let through the modes that apply.
switch (type) {
case VIMM___x___x:
@ -3102,7 +2997,6 @@ error:
}
void ARMXEmitter::VBIC_imm(u32 Size, ARMReg Vd, VIMMMode type, int imm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// Only let through the modes that apply.
switch (type) {
case VIMM___x___x:
@ -3129,7 +3023,6 @@ error:
void ARMXEmitter::VMVN_imm(u32 Size, ARMReg Vd, VIMMMode type, int imm) {
_dbg_assert_msg_(cpu_info.bNEON, "Can't use %s when CPU doesn't support it", __FUNCTION__);
// Only let through the modes that apply.
switch (type) {
case VIMM___x___x:
@ -3187,7 +3080,6 @@ void ARMXEmitter::VREV16(u32 Size, ARMReg Vd, ARMReg Vm)
void ARMXEmitter::VCVTF32F16(ARMReg Dest, ARMReg Src) {
_assert_msg_(cpu_info.bVFPv4, "Can't use half-float conversions when you don't support VFPv4");
if (Dest < Q0 || Dest > Q15 || Src < D0 || Src > D15) {
_assert_msg_(cpu_info.bNEON, "Bad inputs to VCVTF32F16");
// Invalid!
}
@ -3203,7 +3095,6 @@ void ARMXEmitter::VCVTF32F16(ARMReg Dest, ARMReg Src) {
void ARMXEmitter::VCVTF16F32(ARMReg Dest, ARMReg Src) {
_assert_msg_(cpu_info.bVFPv4, "Can't use half-float conversions when you don't support VFPv4");
if (Dest < D0 || Dest > D15 || Src < Q0 || Src > Q15) {
_assert_msg_(cpu_info.bNEON, "Bad inputs to VCVTF32F16");
// Invalid!
}
Dest = SubBase(Dest);

2
Core/MIPS/IR/IRJit.cpp
View File

@ -61,7 +61,7 @@ IRJit::IRJit(MIPSState *mipsState, bool actualJit) : frontend_(mipsState->HasDef
#elif PPSSPP_ARCH(ARM) || PPSSPP_ARCH(ARM64)
opts.unalignedLoadStore = (opts.disableFlags & (uint32_t)JitDisable::LSU_UNALIGNED) == 0;
opts.unalignedLoadStoreVec4 = true;
opts.preferVec4 = cpu_info.bASIMD || cpu_info.bNEON;
opts.preferVec4 = true;
#else
opts.unalignedLoadStore = (opts.disableFlags & (uint32_t)JitDisable::LSU_UNALIGNED) == 0;
// TODO: Could allow on x86 pretty easily...