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Crashfix dumping display lists that start at the start of VRAM (seems to hit this in GTA).

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Add a couple of comments.
This commit is contained in:
Henrik Rydgard 2013-10-07 22:57:44 +02:00
parent 8f620c30ab
commit fc8aa7bd8f
3 changed files with 12 additions and 3 deletions
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3
Common/x64Emitter.h
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@ -643,7 +643,8 @@ public:
void PMAXUB(X64Reg dest, OpArg arg);
void PMINSW(X64Reg dest, OpArg arg);
void PMINUB(X64Reg dest, OpArg arg);
// SSE4 has PMAXSB and PMINSB and PMAXUW and PMINUW too if we need them.
void PMOVMSKB(X64Reg dest, OpArg arg);
void PSHUFB(X64Reg dest, OpArg arg);

5
Core/MIPS/x86/CompVFPU.cpp
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@ -1095,6 +1095,9 @@ void Jit::Comp_Vi2f(MIPSOpcode op) {
// SHUFPS(XMM2, R(XMM3), _MM_SHUFFLE(0, 0, 0, 0)); // XMM2 = S3 S3 S2 S2
// SHUFPS(XMM0, R(XMM2), _MM_SHUFFLE(2, 0, 2, 0)); // XMM0 = S3 S2 S1 S0
// Some punpckwd etc would also work.
// Alternatively, MOVSS and three PINSRD (SSE4) with mem source.
// Why PINSRD instead of INSERTPS?
// http://software.intel.com/en-us/blogs/2009/01/07/using-sse41-for-mp3-encoding-quantization
// Sequence for scattering a SIMD register to sparse registers:
// (Very serial though, better methods may be possible)
@ -1105,7 +1108,7 @@ void Jit::Comp_Vi2f(MIPSOpcode op) {
// MOVSS(fpr.R(sregs[2]), XMM0);
// SHUFPS(XMM0, R(XMM0), _MM_SHUFFLE(3, 3, 2, 1));
// MOVSS(fpr.R(sregs[3]), XMM0);
// On SSE4 we should use EXTRACTPS.
// Translation of ryg's half_to_float5_SSE2
void Jit::Comp_Vh2f(MIPSOpcode op) {

7
GPU/GPUCommon.cpp
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@ -553,7 +553,12 @@ void GPUCommon::SlowRunLoop(DisplayList &list)
PreExecuteOp(op, diff);
if (dumpThisFrame) {
char temp[256];
u32 prev = Memory::ReadUnchecked_U32(list.pc - 4);
u32 prev;
if (Memory::IsValidAddress(list.pc - 4)) {
prev = Memory::ReadUnchecked_U32(list.pc - 4);
} else {
prev = 0;
}
GeDisassembleOp(list.pc, op, prev, temp);
NOTICE_LOG(G3D, "%s", temp);
}