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ARMJIT: Combine to one instruction for load/stores.

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This commit is contained in:
Sacha 2013-02-27 19:45:01 +10:00
parent 2c59de95e9
commit ff14815fda
3 changed files with 43 additions and 24 deletions
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20
Common/ArmEmitter.cpp
View File

@ -542,16 +542,20 @@ void ARMXEmitter::WriteStoreOp(u32 op, ARMReg dest, ARMReg src, Operand2 op2)
Write32(condition | (op << 20) | (3 << 23) | (dest << 16) | (src << 12) | op2.Imm12());
}
void ARMXEmitter::STR (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x40, dest, src, op);}
void ARMXEmitter::STRH(ARMReg dest, ARMReg src, Operand2 op)
void ARMXEmitter::STRH (ARMReg dest, ARMReg src, Operand2 op)
{
u8 Imm = op.Imm8();
Write32(condition | (0x04 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
}
void ARMXEmitter::STRB(ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x44, dest, src, op);}
void ARMXEmitter::STRB (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x44, dest, src, op);}
void ARMXEmitter::STR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | offset);
}
void ARMXEmitter::STRH (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x00 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | (0xB << 4) | offset);
}
void ARMXEmitter::STRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x64 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | offset);
@ -596,10 +600,22 @@ void ARMXEmitter::LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool
{
Write32(condition | (0x61 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | offset);
}
void ARMXEmitter::LDRH (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x01 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | (0xB << 4) | offset);
}
void ARMXEmitter::LDRSH(ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x01 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | (0xF << 4) | offset);
}
void ARMXEmitter::LDRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x65 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | offset);
}
void ARMXEmitter::LDRSB(ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
{
Write32(condition | (0x01 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | (0xD << 4) | offset);
}
void ARMXEmitter::WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList)
{
Write32(condition | (op << 20) | (WriteBack << 21) | (dest << 16) | RegList);

14
Common/ArmEmitter.h
View File

@ -468,19 +468,23 @@ public:
// Memory load/store operations
void LDR (ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRH (ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRSH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRB(ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRBH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRB (ARMReg dest, ARMReg src, Operand2 op2 = 0);
void LDRSB(ARMReg dest, ARMReg src, Operand2 op2 = 0);
// Offset adds to the base register in LDR
void LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void LDRH (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void LDRSH(ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void LDRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void LDRSB(ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void STR (ARMReg dest, ARMReg src, Operand2 op2 = 0);
void STRH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
void STRB(ARMReg dest, ARMReg src, Operand2 op2 = 0);
void STRH (ARMReg dest, ARMReg src, Operand2 op2 = 0);
void STRB (ARMReg dest, ARMReg src, Operand2 op2 = 0);
// Offset adds on to the destination register in STR
void STR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void STRH (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void STRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
void STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);

19
Core/MIPS/ARM/ArmCompLoadStore.cpp
View File

@ -114,17 +114,14 @@ namespace MIPSComp
LDR(gpr.R(rt), R11, R0, true, true);
} else if (o == 37) {
// 16-bit
ADD(R0, R0, R11); // TODO: Merge with next instruction
LDRH(gpr.R(rt), R0);
LDRH(gpr.R(rt), R11, R0, true, true);
} else if (o == 33) {
ADD(R0, R0, R11); // TODO: Merge with next instruction
LDRSH(gpr.R(rt), R0);
LDRSH(gpr.R(rt), R11, R0, true, true);
} else if (o == 36) {
// 8-bit
LDRB(gpr.R(rt), R11, R0, true, true);
} else if (o == 32) {
ADD(R0, R0, R11); // TODO: Merge with next instruction
LDRSB(gpr.R(rt), R0);
LDRSB(gpr.R(rt), R11, R0, true, true);
}
} else {
Comp_Generic(op);
@ -146,12 +143,14 @@ namespace MIPSComp
SetR0ToEffectiveAddress(rs, offset);
}
if (o == 43) {
// 32-bit
STR(R0, gpr.R(rt), R11, true, true);
} else if (o == 40) {
STRB(R0, gpr.R(rt), R11, true, true);
} else if (o == 41) {
ADD(R0, R0, R11); // TODO: Merge with next instruction
STRH(gpr.R(rt), R0);
// 16-bit
STRH(R0, gpr.R(rt), R11, true, true);
} else if (o == 40) {
// 8-bit
STRB(R0, gpr.R(rt), R11, true, true);
}
} else {
Comp_Generic(op);