Brad Smith
59ba9ab973
Fix building on OpenBSD/riscv64.
...
Unbreak on riscv64, we don't have sys/auxv.h or getauxval().
OpenBSD/riscv64 assumes RV64GC, aka RV64IMAFDC.
Our kernel provides no support for the V extension.
2024-04-27 07:44:37 -04:00
Henrik Rydgård
1f129b6dca
Replace "ReadFileToString" with a few semantically clearer wrappers.
2024-01-25 09:55:54 +01:00
Henrik Rydgård
46b25d20a4
Merge pull request #18637 from unknownbrackets/riscv-more
...
Add some more RISC-V extensions to emitter
2023-12-29 19:03:49 +01:00
Unknown W. Brackets
52db66e7ad
riscv: Add vector bitmanip encoding.
2023-12-29 09:42:23 -08:00
Unknown W. Brackets
83dc1c9705
riscv: Add detect flags, not detected yet.
2023-12-29 09:42:23 -08:00
Henrik Rydgård
e3177ac870
Make some global string pointers const, not just the strings.
...
Minor cleanup.
2023-12-29 14:09:45 +01:00
Unknown W. Brackets
030a27f15d
riscv: Stop considering bitmanip "B".
...
Apparently it's not being called B anymore and B is still reserved.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets
0c99d6d3fa
riscv: Workaround Zicsr detection issue.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets
ac40721a64
riscv: Use cpu_features for V detection.
2023-04-29 10:07:50 -07:00
Unknown W. Brackets
63f370916b
riscv: Enable Zba/Zbb by soc compatible.
...
Instead of u74, because apparently some older u74 don't support it.
2023-03-03 03:37:58 +00:00
Unknown W. Brackets
04ce3a0572
riscv: Allow subset of B extension to be used.
2023-02-16 16:09:22 -08:00
Unknown W. Brackets
dcd83c1e47
riscv: Detect Zicsr with cpu_features.
2023-01-29 15:24:41 -08:00
Unknown W. Brackets
09eb509df4
Common: Expose CPU extension list directly.
...
A bit silly to rely on the specific string formatting of a summary.
2023-01-29 15:13:44 -08:00
Unknown W. Brackets
3bc2450b5e
riscv: Add bitmanip instructions to emitter ( #16832 )
...
* riscv: Cleanup emitter, add bitmanip detect.
Better to encode using Funct7::ZERO, and obviously for SRA.
* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
Unknown W. Brackets
82f0502b4e
riscv: Implement CPU feature detection.
2022-12-21 03:12:16 +00:00
Pierce Andjelkovic
9ac4931636
Fix get CPU & CPU Brand
2021-07-31 03:03:13 +10:00
Pierce Andjelkovic
bd8759853b
Fix ABI
2021-07-31 01:50:48 +10:00
Pierce Andjelkovic
0d0e2c44e0
Fix copied mips bugs
2021-07-29 07:47:09 +10:00
Pierce Andjelkovic
d452b0c1f7
No CPU part for RISC-V
2021-07-29 03:26:18 +10:00
Pierce Andjelkovic
d9a3741fcb
RISC-V CPU detect
2021-07-28 21:58:56 +10:00
