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Code Issues Actions 2 Packages Projects Releases Wiki Activity
41,071 Commits 72 Branches 122 Tags 682 MiB
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51 Commits

Author SHA1 Message Date
Henrik Rydgård
e01ca5b057
Logging API change (refactor) (#19324) 
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
 2024-07-14 14:42:59 +02:00
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52db66e7ad riscv: Add vector bitmanip encoding. 2023-12-29 09:42:23 -08:00
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83dc1c9705 riscv: Add detect flags, not detected yet. 2023-12-29 09:42:23 -08:00
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e5467d2706 riscv: Add czero instruction encoding. 2023-12-29 09:42:23 -08:00
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e3c6add63a riscv: Add encoding for Zcb. 2023-12-29 09:42:23 -08:00
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15cb782f85 riscv: Implement Zfa encoding. 
Not yet enabled/detected.
 2023-12-29 09:42:23 -08:00
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fc476020ba riscv: Improve immediate generation. 
Use compressed instructions more, better jumps when outside PC 32-bit
range.
 2023-08-12 09:37:02 -07:00
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4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
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26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
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76e3246065 riscv: Reduce jit codesize a bit. 2023-07-23 18:01:00 -07:00
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47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00
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030a27f15d riscv: Stop considering bitmanip "B". 
Apparently it's not being called B anymore and B is still reserved.
 2023-07-23 14:41:08 -07:00
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e0eace505b riscv: Fix cases of SetRegToImmediate(). 
Was using the wrong value for AUIPC, causing assertion failures and wrong
values.  Also needed to handle sign-extend more carefully.
 2023-07-23 14:41:08 -07:00
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27e60a9f2e riscv: Sum weighted matrices in vertexjit. 
Not yet doing pos/norm, so not used yet.
 2023-02-16 18:32:58 -08:00
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04ce3a0572 riscv: Allow subset of B extension to be used. 2023-02-16 16:09:22 -08:00
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684aa75388 riscv: Include morph in vertexjit. 2023-02-14 20:20:55 -08:00
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1ec33ddc04 riscv: Use __riscv_flush_icache() on Linux. 
This seems to perhaps clear icache on all harts.  Otherwise crashing is
seen.  Not sure what to do on other platforms.
 2023-02-14 19:59:42 -08:00
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0b05d20c0a riscv: Fix poison with compressed instructions. 2023-02-12 13:02:55 -08:00
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89c18d8077 riscv: Cleanup missing Poison, Crash. 2023-02-12 12:10:29 -08:00
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a0ef9ce103 riscv: Add half-float encodings. 
These are simple.
 2023-01-29 16:31:01 -08:00
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dcd83c1e47 riscv: Detect Zicsr with cpu_features. 2023-01-29 15:24:41 -08:00
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riscv: Add bitmanip instructions to emitter (#16832) 
* riscv: Cleanup emitter, add bitmanip detect.

Better to encode using Funct7::ZERO, and obviously for SRA.

* riscv: Add bitmanip instructions to emitter.
 2023-01-22 21:37:47 +01:00
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2aeee83971 riscv: Add vector transfer instructions. 2023-01-22 00:17:40 -08:00
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c99eb18f33 riscv: Add vector mask instructions. 2023-01-21 23:43:28 -08:00
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88de043329 riscv: Add vector reduce instructions. 2023-01-21 22:35:38 -08:00
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2a7bdbf802 riscv: Add vector float move/compare/unary. 2023-01-21 22:05:13 -08:00
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f0796676fd riscv: Add vector float arith/mul funcs. 
Including all the fused multiplies.
 2023-01-21 20:48:49 -08:00
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a1ca291362 riscv: Add vector fixed-point arith instructions. 2023-01-21 20:23:10 -08:00
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a313e440b4 riscv: Add vector integer move/broadcast. 2023-01-21 19:46:50 -08:00
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6f78f2a2d2 riscv: Add vector integer muliplies. 2023-01-21 19:46:34 -08:00
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b3be901557 riscv: Add vector bitwise/compare funcs. 2023-01-21 19:36:22 -08:00
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6fa50eaa82 riscv: Add vector int add/sub and many encodings. 2023-01-21 19:36:11 -08:00
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bfd60a67ad riscv: Add vector load/store ops. 2023-01-21 19:36:11 -08:00
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82f0502b4e riscv: Implement CPU feature detection. 2022-12-21 03:12:16 +00:00
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5916b3f3a8 riscv: Fix compile error on clang. 
This also works on gcc.
 2022-12-21 03:07:47 +00:00
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1810692236 Global: Cleanup some type/range checks. 2022-12-10 21:13:37 -08:00
Sprite
0ed86188b0 Fix const pointer conversion error for RISC-V 2022-09-15 23:53:19 +08:00
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08d82ec15b riscv: Emit compressed instructions. 
Includes automatically using compressed, optionally.
 2022-08-27 15:44:19 -07:00
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946080206d riscv: Improve sign reduce/immediate readability. 2022-08-27 15:44:18 -07:00
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c807d459f6 riscv: Emit ADD/SUB/etc. for ADDW/SUBW/etc. on R32. 
No need to complicate code, we can just write ADDW() and expect it to work
on R32 (if ever motivated to support it.)
 2022-08-27 15:44:18 -07:00
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c81d887a86 riscv: Include an LI helper in the emitter. 
Can be used for integers and floats.
 2022-08-27 15:44:18 -07:00
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4a93647acb riscv: Emit CSR manipulation instructions. 2022-08-25 21:20:49 -07:00
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b5755b6cf7 riscv: Validate FixupBranch usage better. 
Also avoid FixupBranch alignment issues.
 2022-08-25 21:20:49 -07:00
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591de6be1d riscv: Emit float instructions. 2022-08-25 21:19:28 -07:00
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53693072d2 riscv: Emit atomic operations. 2022-08-25 21:19:28 -07:00
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c66d02d4db riscv: Emit mul/div instructions. 2022-08-25 21:19:28 -07:00
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00280ab2ad riscv: Emit fence and 64-bit instructions. 2022-08-25 21:19:28 -07:00
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49ec8a207d riscv: Emit 32-bit 3-op instructions, validate GPR. 2022-08-25 21:19:27 -07:00
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1c35cfb325 riscv: Emit 32-bit load/store and imm ops. 2022-08-25 21:19:27 -07:00
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1dab9d1875 riscv: Emit standard B/U/J type ops. 2022-08-25 21:19:27 -07:00