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39,584 Commits 72 Branches 122 Tags 682 MiB
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Commit Graph

922 Commits

Author SHA1 Message Date
Henrik Rydgård
126d88ecfc Back out clearly inconsequential/useless .reserve() calls 2023-12-29 08:27:56 +01:00
Henrik Rydgård
e5af1f8bd0
Merge pull request #18560 from unknownbrackets/replacement-slice 
HLE: Slice the very slow memset/memcpy variants
 2023-12-17 12:35:48 +01:00
Unknown W. Brackets
053831bf4d HLE: Add mechanics for sliced replacements. 2023-12-16 09:08:58 -08:00
Unknown W. Brackets
5311997753 x86jit: Correct downcount on replacement in IR. 2023-12-16 08:10:29 -08:00
Herman Semenov
b871e76d05 [Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible 2023-12-15 13:59:19 +03:00
Henrik Rydgård
76f0c6cab4
Merge pull request #18305 from unknownbrackets/x86-ir-vcmp 
x86jit: Fix IR vcmp all bit
 2023-10-04 07:48:42 +02:00
Unknown W. Brackets
f1a9e39ce9 x86jit: Fix IR vcmp all bit. 2023-10-03 17:46:29 -07:00
Unknown W. Brackets
521335cb2a x86: Fix 32-bit IR jit block entry. 2023-10-02 20:26:07 -07:00
Unknown W. Brackets
00c80cea6e irjit: Optimize offset logging during compile. 
As I guessed, this was expensive.  using a vector and reserve isn't very.
It's nice to keep this before logBlocks_ is > 0, in case it's set mid
block.
 2023-09-30 15:56:18 -07:00
Henrik Rydgård
51d5026792 WriteExit: Assert on bad exit numbers 2023-09-26 19:39:48 +02:00
Henrik Rydgård
9fffa33eee
Merge pull request #18234 from unknownbrackets/x86-ir-transfer 
x86jit: Perform vector transfers instead of flushing to memory
 2023-09-26 09:28:05 +02:00
Unknown W. Brackets
38e5b33a53 x86jit: Prefer BLENDPS to INSERTPS. 
It's faster, this performs better.
 2023-09-25 22:12:48 -07:00
Henrik Rydgård
51456980db
Merge pull request #18121 from unknownbrackets/jit-ir-profiler 
IR: Add mini native jit MIPS block profiler
 2023-09-25 09:04:55 +02:00
Unknown W. Brackets
9b2fa46861 IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
Unknown W. Brackets
05786f5719 x86jit: Correct spill on IR lane extract. 2023-09-24 19:06:06 -07:00
Unknown W. Brackets
685d2acffe x86jit: Retain old lanes when there's space. 2023-09-24 17:31:25 -07:00
Unknown W. Brackets
46e704f879 x86jit: Cleanup and refactor transfer. 2023-09-24 16:58:41 -07:00
Unknown W. Brackets
d9f6bae1ff x64jit: Initial reg transfer. 2023-09-24 16:28:29 -07:00
Henrik Rydgård
06a1f0b72c
Merge pull request #18226 from unknownbrackets/x86-ir-breakpoints 
x86jit: Improve memory breakpoint speed
 2023-09-25 00:47:22 +02:00
Unknown W. Brackets
da013ee105 x86jit: Fix asm jitbase displacement check. 2023-09-24 12:11:00 -07:00
Unknown W. Brackets
7d0f2e43b6 irjit: Fix safety of kernel bit memory addresses. 2023-09-24 10:18:55 -07:00
Henrik Rydgård
2ba63c65f2
Merge pull request #18227 from unknownbrackets/x86-ir-flush 
x86jit: Flush floats together if possible
 2023-09-24 17:27:38 +02:00
Unknown W. Brackets
d36728e532 x86jit: Load common float vals from constants. 2023-09-24 08:01:08 -07:00
Unknown W. Brackets
decccf199a x86jit: Flush floats together if possible. 2023-09-24 08:01:05 -07:00
Unknown W. Brackets
9742aaaffe x86jit: Use MOVAPS directly when we can. 
May help older processors or reduce total bytes.
 2023-09-24 08:01:02 -07:00
Unknown W. Brackets
e433a8be4a arm64jit: Speed up memchecks, add validation. 2023-09-24 07:42:11 -07:00
Unknown W. Brackets
5929aaae85 x86jit: Speed up safe memory checks. 2023-09-24 07:06:57 -07:00
Unknown W. Brackets
017d0d4b17 x86jit: Improve memory breakpoint speed. 
This helps a lot compared to before.
 2023-09-24 07:06:57 -07:00
Unknown W. Brackets
3e20a5802f x86jit: Describe constants better. 2023-09-24 06:46:42 -07:00
Henrik Rydgård
1c58617392
Merge pull request #18208 from unknownbrackets/x86-ir-float 
x86jit: Speed up float to int conversions
 2023-09-24 09:30:00 +02:00
Henrik Rydgård
ac3139b8ee
Merge pull request #18213 from unknownbrackets/x86-ir-fcmp 
IR: Improve fcmp/vfpu compare jit
 2023-09-24 09:29:14 +02:00
Unknown W. Brackets
6d41f15f0d x86jit: Implement FSign. 2023-09-23 22:08:17 -07:00
Unknown W. Brackets
06ec41d1de x86jit: Implement fcr31/break related ops. 2023-09-23 22:01:22 -07:00
Unknown W. Brackets
3a705d9470 x86jit: Implement BSwap16. 2023-09-23 22:01:09 -07:00
Unknown W. Brackets
580c9a634b x86jit: Implement ReverseBits. 2023-09-23 22:00:58 -07:00
Unknown W. Brackets
24da5a3ba2 irjit: Small simplification to regcache. 2023-09-23 22:00:49 -07:00
Unknown W. Brackets
15f01b13a2 x86jit: Small tweak for SltU zero, x. 2023-09-23 22:00:38 -07:00
Unknown W. Brackets
14e2e1ed62 x64jit: Optimize FCmpVfpuAggregate. 2023-09-23 14:31:46 -07:00
Unknown W. Brackets
c5d896a9d7 x86jit: Speed up c.eq.s. 2023-09-23 14:31:18 -07:00
Unknown W. Brackets
1c81d47dd4 x86jit: Speed up float to int conversions. 2023-09-23 13:28:58 -07:00
Henrik Rydgård
e64d1e94fe add reporting to the invalid replacement op 2023-09-23 11:39:20 +02:00
Henrik Rydgård
8a90e94e74 Add an assert to try to track down a mysterious reported crash. 2023-09-21 12:08:16 +02:00
Henrik Rydgård
92d1a66565
Merge pull request #18165 from unknownbrackets/x64-ir-bmi2 
x86jit: Fix flush for special-purpose reg
 2023-09-17 19:38:31 +02:00
Unknown W. Brackets
07150b566a x86jit: Fix flush for special-purpose reg. 2023-09-17 09:37:57 -07:00
Unknown W. Brackets
1fad623397 x86jit: Fix spill on sc in longer block. 2023-09-11 22:29:46 -07:00
Henrik Rydgård
23aedf1e63 More sensible approach to the sc problem that broke Beats 2023-09-11 16:07:21 +02:00
Henrik Rydgård
accd9b1f2c sc instruction: Make sure the rt register is mapped. Fixes Beats. 2023-09-11 14:18:58 +02:00
Henrik Rydgård
a84f08e55e Typo fix 
See #18080
 2023-09-06 11:21:41 +02:00
Henrik Rydgård
1bfa566b3d
Merge pull request #18081 from unknownbrackets/arm64jit-float 
arm64jit: Implement some float compares and conversions
 2023-09-06 10:11:56 +02:00
Unknown W. Brackets
97d9a7f07f arm64jit: Implement FCmp. 2023-09-06 00:09:26 -07:00