Henrik Rydgård
5ee04ce403
SDL: Break out event processing from main loop
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Makes things a bit easier to work with.
2023-08-08 12:28:42 +02:00
Henrik Rydgård
bcae36d8cb
Merge NativeUpdate and NativeRender, we always call them together.
2023-08-07 22:50:57 +02:00
Henrik Rydgård
096c168dd7
Add yield() function to tell the CPU that we're busy-waiting (rare) ( #17862 )
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* Add yield() function to tell the CPU that we're busy-waiting (rare)
Use it only for the busy-wait in lag sync, which only happens in
Windows.
* Buildfix attempt
2023-08-07 21:38:03 +02:00
Henrik Rydgård
e9431d0d1e
Merge pull request #17859 from unknownbrackets/irjit-vec4
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irjit: Use Vec4 a bit more
2023-08-06 23:05:33 +02:00
Unknown W. Brackets
3dc71cff75
irjit: Keep a couple more ops in Vec4.
2023-08-06 13:46:24 -07:00
Unknown W. Brackets
6a1dbd4cde
irjit: Allow Vec4 to be used with masks.
2023-08-06 13:46:24 -07:00
Unknown W. Brackets
2b964fd3b0
irjit: Handle more common Vec4 prefix cases.
2023-08-06 13:38:00 -07:00
Unknown W. Brackets
79ca880ac7
irjit: Implement vqmul, add Vec4Blend.
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Should be useful more places.
2023-08-06 13:38:00 -07:00
Unknown W. Brackets
85ee7c85c1
irjit: Allow masked vneg.q.
2023-08-06 13:38:00 -07:00
Henrik Rydgård
d90dbcb28e
Merge pull request #17857 from unknownbrackets/ir-vfpuctrl
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irjit: Fix mfvc eating prefixes
2023-08-06 17:56:22 +02:00
Unknown W. Brackets
a32889d3ca
irjit: Consistently dirty vfpuctrl in IR.
2023-08-06 08:36:19 -07:00
Unknown W. Brackets
a29a35b91a
irjit: Fix mfvc eating prefixes.
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It doesn't and shouldn't, which is why it's marked as not.
2023-08-06 08:28:25 -07:00
Henrik Rydgård
70622e0d4e
Merge pull request #17853 from Nemoumbra/buildfix
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Buildfix for VS2017
2023-08-06 14:29:04 +02:00
Nemoumbra
c2f9ae2e16
Buildfix for VS2017
2023-08-06 15:06:54 +03:00
Henrik Rydgård
ea659319b2
Merge pull request #17852 from unknownbrackets/riscv-centralize
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IR: centralize common parts of native backend
2023-08-06 10:54:53 +02:00
Unknown W. Brackets
93e3d35f5d
irjit: Move more to IRNativeBackend, split.
2023-08-06 00:16:43 -07:00
Unknown W. Brackets
691799a0ca
irjit: Centralize native jit compile dispatch.
2023-08-03 23:14:58 -07:00
Henrik Rydgård
a32249a3cf
Move DebugOverlay rendering to the overlay screen, allowing drawing it on top of the menu
2023-08-03 16:19:18 +02:00
Henrik Rydgård
ece6a505b3
Merge pull request #17837 from hrydgard/frame-history
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Vulkan: Keep track of a short history of some timestamps in each frame
2023-08-02 17:06:55 +02:00
Hoe Hao Cheng
805821e01e
Core: decouple UpdateScreenScale from preprocessor defines
2023-08-02 22:34:46 +08:00
Hoe Hao Cheng
0d7a1831b6
sdl: support HiDPI on wayland
2023-08-02 22:34:46 +08:00
Henrik Rydgård
cda59e8510
Vulkan: Keep track of some timestamps in a frame
2023-08-02 16:25:17 +02:00
Henrik Rydgård
0b4fee1259
One too much
2023-08-02 14:07:47 +02:00
Henrik Rydgård
c3511529e4
Somehow forgot to delete some unused bools
2023-08-02 14:07:05 +02:00
Henrik Rydgård
fc6879674e
Refactor overlays into an enum
2023-08-02 13:03:04 +02:00
Henrik Rydgård
9a8919810b
Translation cleanups
2023-08-01 13:04:52 +02:00
Henrik Rydgård
f45176fd25
Allow configuring in which corner achievement notifications can show up.
2023-08-01 12:52:09 +02:00
Henrik Rydgård
1071e1f248
Move towards separate types for leaderboard events
2023-08-01 11:57:28 +02:00
Henrik Rydgård
d268dd639a
Move the ScreenEdgePosition enum to a more appropriate location
2023-08-01 01:01:57 +02:00
Henrik Rydgård
3563d625b9
Allow configuring the location on-screen of leaderboard trackers.
2023-08-01 00:28:54 +02:00
Henrik Rydgård
48d577014a
Refactor the on-screen display to be more customizable
2023-08-01 00:28:54 +02:00
Henrik Rydgård
f39b9640b7
Rename the ChatPosition enum to a ScreenEdgePosition enum class (for future use)
2023-08-01 00:28:54 +02:00
Unknown W. Brackets
0d0029fc9d
riscv: Add bitmanip ops to disasm.
2023-07-30 17:45:36 -07:00
Unknown W. Brackets
c24dca12bb
Build: Fix link issue for rv64 disasm.
2023-07-30 16:06:55 -07:00
Unknown W. Brackets
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit
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riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
Henrik Rydgård
fa2b831dbc
Merge pull request #17814 from unknownbrackets/riscv-jit-debug
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riscv: Implement block debug interface
2023-07-30 23:42:14 +02:00
Henrik Rydgård
fa558b5b71
Merge pull request #17813 from unknownbrackets/riscv-jit-fixes
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Fix some typos and mistakes in RISC-V jit
2023-07-30 23:41:13 +02:00
Henrik Rydgård
100f7c838e
Merge pull request #17812 from unknownbrackets/irjit-floats
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Cleanup IR cond move flag, fmov to self
2023-07-30 23:36:37 +02:00
Unknown W. Brackets
f870271011
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
Unknown W. Brackets
020706f545
riscv: Implement float saturate clamping.
2023-07-30 14:24:12 -07:00
Unknown W. Brackets
45d44c1d4f
riscv: Implement block debug interface.
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This gives us the target disasm in jit compare, bloat, etc.
2023-07-30 14:21:43 -07:00
Unknown W. Brackets
5ef4b2b5fa
riscv: Fix assert when flushing not mapped reg.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
9f917488c3
riscv: Fix PC in disassembly.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
e34736fbb2
riscv: Reduce norms in Slt/Sltu overlap cases.
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We can skip an SEXT.W in common cases where the dest and src overlap.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
d1dc346899
riscv: Fix pointer add/sub.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
09f3842a32
riscv: Fix VFPU compare typos.
2023-07-30 14:19:28 -07:00
Unknown W. Brackets
f3240393fa
irjit: Use vf for vfpu regs, v0 is a gpr.
2023-07-30 14:16:17 -07:00
Unknown W. Brackets
6819acd29f
irjit: Fix flag on float cond move.
2023-07-30 14:16:17 -07:00
Unknown W. Brackets
5db6b11ef2
irjit: Cleanup self-fmovs.
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These were sometimes getting emitted.
2023-07-30 14:16:17 -07:00
Henrik Rydgård
f0fd9e85aa
Try dirtying CULL_PLANES in Execute_BoundingBox in SoftGPU
2023-07-30 18:35:18 +02:00
