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4681 Commits

Author SHA1 Message Date
pal1000
5efc4474b0 Fixed pull 4510, this should work. 2013-11-11 17:14:21 +02:00
pal1000
6e67494db0 Cwcheat: Allow comments in cheat files starting with // mainly for writing cheat usage guidelines 2013-11-11 12:01:44 +02:00
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7e19933f64 x86jit: Try predicting branch continues. 
Still doesn't seem to work.  Something like a 4% gain in Star Ocean was
the best I saw...
 2013-11-10 22:50:23 -08:00
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bb960480c8 x86/armjit: Stop compiling on a jump to invalid. 2013-11-10 21:59:50 -08:00
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fd38b10ab6 x86jit: Rename imm funcs to match armjit. 2013-11-10 21:59:49 -08:00
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359110f010 x86/armjit: Add jump following (off by default.) 
Inlines function calls up to a certain extent.  Allows us to get
immediates all the way to a syscall, for example, usually.

Not sure if faster.
 2013-11-10 21:59:49 -08:00
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aacb31bc18 armjit: Copy over (disabled) immbranch optim. 
This does a little loop unrolling.  Costs a bit more cache space, but
avoids flushing regs for longer.

Not enabled.
 2013-11-10 21:59:48 -08:00
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92ecff4396 armjit: keep track of instructions in jitstate. 
To match x86.
 2013-11-10 21:59:48 -08:00
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8ceaafc159 armjit: Verify free space while compiling. 2013-11-10 21:59:48 -08:00
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ca7b2b554b armjit: fix major typo breaking mult/multu. 2013-11-10 21:54:44 -08:00
Henrik Rydgård
a1196399ef Merge pull request #4503 from unknownbrackets/armjit-imms 
Retain immediates in the armjit, optimize similar imms
 2013-11-10 17:22:20 -08:00
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e1fffdb37a armjit: Don't reload an armreg ptr marked noinit. 2013-11-10 16:43:38 -08:00
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67eaa2fd1c armjit: Optimize immediate load/stores in a row. 2013-11-10 16:32:48 -08:00
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bc0a846475 armjit: Optimize imm addresses (could do better...) 2013-11-10 16:30:20 -08:00
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c63560c0dd armjit: Try to find imms to optimize a reg load. 
This way we skip the MOVW/MOVT and go for one op only.
 2013-11-10 16:20:34 -08:00
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7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
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d092f7dd2d armjit: Remember reg imm values even after flush. 
This way, we can base other imm values off them, or even do imm math using
them.  We can also avoid re-flushing an imm.
 2013-11-10 15:50:14 -08:00
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7f9cbc0f10 armjit: Minor cleanup and logging tweaks. 2013-11-10 15:12:40 -08:00
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455a7e090d Compile the cache instruction to nothing. 
Was showing up in a few profiles, does nothing currently.
 2013-11-10 14:38:10 -08:00
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1cc68f50ca armjit: Small optimization to syscall instr. 2013-11-10 14:38:10 -08:00
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b30928036e armjit: Avoid flushing an imm in beq/bne/etc. 
We might be able to STMIA it instead.
 2013-11-10 14:38:10 -08:00
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285ec1fad5 armjit: Implement mult/multu for immediates. 
Uncommon, but may reduce instructions a bit.
 2013-11-10 14:38:09 -08:00
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3a8f0598c4 x86jit: Implement wsbh/wsbw. 2013-11-10 14:38:09 -08:00
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9bec82873c armjit: inline byteswaps of imm values. 2013-11-10 14:38:08 -08:00
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06c8cb9174 armjit: Do shifts with imms as much as possible. 
This may even make an imm operand2 safe that wasn't before.
 2013-11-10 14:38:08 -08:00
Sacha
f29d9c0bf9 Blackberry: fix freezing due to overflow of nanoseconds in timer. 2013-11-11 04:53:08 +10:00
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b2c2a87511 Fix omitted CC_AL reset, fixes #4498. 
Was breaking non-fastmem lwl/lwr/etc.
 2013-11-10 09:24:40 -08:00
Henrik Rydgård
cc23635843 Merge pull request #4495 from unknownbrackets/multithread 
Fix some issues in multithreading on Android
 2013-11-10 01:56:50 -08:00
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d6048dc646 Don't burn the cpu while idle in multithread. 2013-11-09 23:08:45 -08:00
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113146302b Don't schedule a finish event when not running. 
Otherwise it'll get it when it does run, and stop early.
 2013-11-09 23:08:44 -08:00
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afafa5fcd6 Make sure the gpu thread has a chance to run. 
If the scheduler puts it on the same core, it may not even do anything
before we check if the framebuffer is dirty, so SyncThread will quit since
it's not even running.

Instead, let's wait until it's at least done something.
 2013-11-09 23:08:28 -08:00
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879060f008 Use a CORE_POWERUP state when starting. 
Otherwise, we could startup in CORE_POWERDOWN in a second game, which is
confusing.
 2013-11-09 23:07:52 -08:00
shenweip
0a9cf9b1bc Turn up logging. 2013-11-10 10:40:56 +08:00
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b310edc5f8 Fix typo in ARM debug build. 2013-11-09 15:58:27 -08:00
Henrik Rydgard
d1c012d75e ARM: Open up all 32 accessible VFP registers if NEON is available. 2013-11-09 20:18:20 +01:00
Henrik Rydgård
70a239ba47 Merge pull request #4486 from unknownbrackets/debugger 
Use a shortcut for copying instructions, enable G3D log always
 2013-11-09 11:08:12 -08:00
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712b582d26 Remove coreParam.disableG3Dlog and enableDebugging. 
One was uninitialized, the other one unused.
 2013-11-09 11:02:12 -08:00
Henrik Rydgard
0a844ce98d Delete functions for vsge and vslt, these have been rolled into VecDo3 2013-11-09 19:29:52 +01:00
Henrik Rydgard
63334698e1 Add temporary setting to disable the vertex decoder jit while we debug it 2013-11-09 18:16:26 +01:00
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a3a061a69f armjit: Optimize a division by a power of two. 
These really happen.
 2013-11-09 08:43:53 -08:00
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1776c85882 armjit: Implement a software divide for divu. 
It's not actually that much code.
 2013-11-09 08:43:52 -08:00
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b2a240d105 armjit: Implement msub/msubu. 2013-11-09 08:43:52 -08:00
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3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
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4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
Henrik Rydgård
e90f7f360d Merge pull request #4480 from unknownbrackets/perf 
Flush regs using STMIA if possible, plus imm adjustments (armjit)
 2013-11-09 08:41:25 -08:00
Henrik Rydgard
06ce01ea04 Remove erroneous comment. 2013-11-09 17:34:52 +01:00
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54168b173e armjit: Clean up some magic numbers. 2013-11-09 08:25:08 -08:00
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6038d96b46 armjit: Flush regs using STMIA where possible. 2013-11-09 08:25:07 -08:00
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e686ff59bf armjit: Allocate regs in preferred slots. 
This may allow better flushing.  Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
 2013-11-09 08:25:07 -08:00
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cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00