Unknown W. Brackets
d3c06266c5
jit: Fix conditional disable flags.
2021-01-09 11:50:32 -08:00
Henrik Rydgård
4c034ce988
Make all the Comp_Cache implementations the same.
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We have the informative comments in the interpreter implementation
anyway.
2020-10-16 09:13:41 +02:00
Unknown W. Brackets
419c1fbd73
Jit: Respect flags for jit types and features.
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Left some free space for more.
2019-02-03 14:57:08 -08:00
Unknown W. Brackets
b6bb0159e3
irjit: Remove Comp_ITypeMemLR.
2018-01-09 18:06:25 -08:00
Unknown W. Brackets
d27e428659
irjit: Convert lwr and friends to easier code.
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This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
2018-01-07 21:06:00 -08:00
Unknown W. Brackets
6dda053365
irjit: Add dedicated ops for lwl/swl and friends.
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Temporarily removes optimizations.
2018-01-07 21:05:57 -08:00
Unknown W. Brackets
64b57a0329
irjit: Fix swr typo.
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Shifting the wrong direction - oops.
2018-01-03 08:14:25 -08:00
Unknown W. Brackets
3abcc4d6d8
irjit: Implement lwl/lwr/swl/swr.
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This is very similar to the arm64jit implementation.
2018-01-01 08:38:13 -08:00
Unknown W. Brackets
905d2c2da6
irjit: Cleanup some invalid op handling.
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And log blocks the same way as other backends.
2018-01-01 08:38:11 -08:00
Unknown W. Brackets
4578c3cb54
jit-ir: Implement memory breakpoints.
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These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
Henrik Rydgard
f636b2a315
Minor build and other fixes
2016-05-13 19:31:27 +02:00
Henrik Rydgard
558bb197c7
More VFPU
2016-05-09 23:47:56 +02:00
Henrik Rydgard
e806c369b2
Separate the IR frontend from the IR "Jit"
2016-05-09 19:57:18 +02:00
Henrik Rydgard
a33f8b68c6
ir-jit: Get rid of the regcache. Should be replaced with optimization passes.
2016-05-07 23:12:53 +02:00
Henrik Rydgard
4acf85aa06
It's kind of starting to run
2016-05-07 17:37:19 +02:00
Henrik Rydgard
d399c4a470
Initial commit for IRJit
2016-05-07 13:58:29 +02:00
