Unknown W. Brackets
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9c9330a207
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riscv: Implement float conditional move.
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2023-07-30 00:02:10 -07:00 |
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Unknown W. Brackets
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70ff18a463
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riscv: Implement count leading zeros.
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2023-07-30 00:02:10 -07:00 |
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Unknown W. Brackets
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a5671bc716
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riscv: Add simple debug log of missed ops.
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2023-07-30 00:02:10 -07:00 |
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Unknown W. Brackets
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6d4fb949c2
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riscv: Implement float compare ops.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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6b632a103d
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riscv: Implement FSin/similar.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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921bd2391c
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riscv: Implement vi2s.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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e2765db4dc
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riscv: Implement division.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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f65b6fdb20
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riscv: Remove incomplete block check.
It shouldn't be necessary and bad things would happen anyway if it did.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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8d60c10a64
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riscv: Use jit address offsets directly.
We'll have IR able to use block number or target offset.
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2023-07-29 19:02:15 -07:00 |
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Henrik Rydgård
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4aa2b1fcac
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Merge pull request #17783 from unknownbrackets/riscv-jit
Implement float/vec operations in RISC-V jit
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2023-07-28 08:38:19 +02:00 |
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Unknown W. Brackets
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a181f6d5b8
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riscv: Add a comment for FMUL testing later.
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2023-07-27 22:16:29 -07:00 |
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Unknown W. Brackets
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5122b0c78e
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riscv: Cleanup unnecessary fcr31 func.
Don't need this, we use DYNAMIC.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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0c9dce8ba8
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riscv: Implement vec4 dot.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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23e9dffc68
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riscv: Implement vec4 shuffle and init.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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4e17c59cc2
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riscv: Implement simple vec4 ops via floats.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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df313bd296
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riscv: Fix rounding mode setting.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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9157d992ac
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jit-ir: Implement cfc1/ctc1.
This makes it so we can track rounding mode changes.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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ca7a520a19
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riscv: Implement FMul.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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9a9b371856
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riscv: Implement FSign using FCLASS.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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05360d5c7a
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riscv: Implement simplest float ops.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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bb6fdd0246
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riscv: Add floating point load/stores.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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7071884a47
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riscv: Handle rounding mode and ctrl transfers.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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067a033dc0
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riscv: Add FPU regcache.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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c3db3d5187
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arm64jit: When rouding unset, use nearest.
The 0/default rounding mode is nearest, not toward zero.
We set hasSetRounding only when fcr31 has a non-zero rounding mode or
flush to zero set.
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2023-07-25 20:30:05 -07:00 |
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Unknown W. Brackets
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a8edf5fa24
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riscv: Reduce bloat in jit fallbacks.
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2023-07-25 19:42:04 -07:00 |
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Unknown W. Brackets
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b97b7f3663
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riscv: Make some regcache methods private.
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2023-07-25 19:42:04 -07:00 |
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Unknown W. Brackets
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3383d5b93a
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Merge pull request #17751 from unknownbrackets/riscv-jit
Initial RISC-V jit based on IR
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2023-07-25 00:42:22 -07:00 |
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Henrik Rydgård
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a72c4aa383
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Actually fix the race condition. Can't do any initialization step while waiting.
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2023-07-24 12:08:15 +02:00 |
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Henrik Rydgård
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3ae520c35d
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RetroAchievements: Fix another race condition, improve logging.
Seems to help the frontend problem.
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2023-07-24 12:00:16 +02:00 |
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Unknown W. Brackets
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b6f83ca969
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riscv: Cleanup some pointerification flags.
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2023-07-23 21:17:55 -07:00 |
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Unknown W. Brackets
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18c48681a8
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riscv: Implement multiply instructions.
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2023-07-23 18:01:50 -07:00 |
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Unknown W. Brackets
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7f4689e8fa
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riscv: Use direct SLI/SLIU instructions.
Derp, I forgot these existed on RISC-V for a moment.
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2023-07-23 18:01:46 -07:00 |
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Unknown W. Brackets
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ca15fa7061
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riscv: Enable jit by default.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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4100767b5e
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riscv: Optimize SetConst a bit.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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f7f7531500
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riscv: Fix min/max normalization.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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34bfe93ea5
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riscv: Fix block lookup issues.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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92694e765f
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riscv: Implement conditional moves.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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2c7da94bd1
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riscv: Implement shifts and compares.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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5ed2f0d559
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riscv: Implement logic ops.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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94be343591
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riscv: Try to keep regs normalized, track.
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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7aafa11d24
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riscv: Implement conditional exits.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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8ee73264bf
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riscv: Correct depointerify on FlushAll().
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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720f868a10
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riscv: Use R_RA as a temporary for calls.
This is the most logical thing, since we're about to write it anyway.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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76e3246065
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riscv: Reduce jit codesize a bit.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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d31eded9ba
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riscv: Allow dirty pointers, explicitly.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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624caa2dea
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riscv: Implement the simplest exits.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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1dfedde741
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riscv: Avoid needless save/load around compile.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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165169eb31
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riscv: Implement load and store ops.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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c2da7d18bb
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riscv: Stub out more IR compilation categories.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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05a2789cf4
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riscv: Implement some simple assign instructions.
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2023-07-23 18:01:00 -07:00 |
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