Henrik Rydgård
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d15a6cf6bf
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Merge pull request #11990 from m4xw/master
Band-Aid for libretro Savestate load
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2019-04-24 11:00:47 +02:00 |
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M4xw
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00bf914ce4
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Band-Aid for libretro Savestate load
Proper would be using PPSSPP's Queue.
This will need frontend extensions to do it sanely.
Fixes #11429 (mitigate for now)
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2019-04-23 17:35:24 +02:00 |
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Henrik Rydgård
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f6fe917615
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Update gradle stuff again
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2019-04-21 11:10:31 +02:00 |
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Henrik Rydgård
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091c475fec
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Merge pull request #11970 from itstake/master
Added IO Timing Method option for RetroArch PPSSPP Core.
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2019-04-20 17:22:31 +02:00 |
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ITSTAKE
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f7aed9a754
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Fix typo again
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2019-04-20 18:02:09 +09:00 |
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Unknown W. Brackets
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8d4ab57b46
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Oops, got these backwards.
Surprising this didn't break as much as expected. Mostly broke the 60 FPS
limit hack.
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2019-04-16 17:36:29 -07:00 |
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Henrik Rydgård
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40f1542798
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Update ffmpeg and lang submodules
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2019-04-16 21:21:52 +02:00 |
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Henrik Rydgård
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dcd2ff03b0
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Merge pull request #11971 from unknownbrackets/power
Correct cpu/pll/bus hz update and rescheduling
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2019-04-16 09:41:43 +02:00 |
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ITSTAKE
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5ee7d73be8
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Fix typo
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2019-04-15 14:07:19 +00:00 |
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Henrik Rydgård
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057e720b28
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Merge pull request #11972 from m4xw/aarch64_masking
Masked PSP Memory support for the AArch64 Dynarec
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2019-04-15 12:43:40 +02:00 |
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M4xw
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b9352354c9
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Masked PSP Memory support for the AArch64 Dynarec
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2019-04-15 12:07:57 +02:00 |
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Unknown W. Brackets
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ad299ca92d
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Power: Match reschedule timing better.
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2019-04-14 15:06:32 -07:00 |
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Unknown W. Brackets
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bc4a203fcf
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Power: Correct hz on update and improve resched.
It only reschedules when the PLL changes, which changes in steps. This
also reads back much more accurate Mhz for each of PLL, CPU, and bus.
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2019-04-14 14:51:35 -07:00 |
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ITSTAKE
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f038573d48
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Added IO Timing Method option.
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2019-04-13 19:31:10 +09:00 |
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Henrik Rydgård
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54e102cfad
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Merge pull request #11965 from psyberpunk/master
Update controller data base ps3 clone controller
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2019-04-10 21:06:02 +02:00 |
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psyberpunk
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d79d829a1d
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Update controller data base ps3 clone controller
Update controller data base ps3 clone controller
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2019-04-10 08:51:47 -05:00 |
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Henrik Rydgård
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b56c66e889
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Merge pull request #11964 from unknownbrackets/gpu-stencil-blend
GPU: Improve non dual source stencil replace
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2019-04-08 01:06:54 +02:00 |
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Unknown W. Brackets
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00d088ab58
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GPU: Improve non dual source stencil replace.
If we're replacing with a constant FF, we can make it work more often.
Fixes #11249.
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2019-04-07 15:20:56 -07:00 |
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Henrik Rydgård
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b5db387bfb
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Merge pull request #11948 from unknownbrackets/vfpu
Make vfad/vavg/vtfm ops more accurate
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2019-04-04 09:31:20 +02:00 |
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Unknown W. Brackets
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ec7cffa847
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interp: Handle vtfm/vhtfm prefixes properly.
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2019-04-02 18:46:39 -07:00 |
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Unknown W. Brackets
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442d6450bb
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interp: Correct prefixes on vfad and vavg.
Including write mask, which didn't work before.
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2019-04-02 18:46:39 -07:00 |
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Henrik Rydgård
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4d580c32c4
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Merge pull request #11959 from unknownbrackets/vfpu-chunk8
Improve prefixes for vwbn/vlgb/vmin/vmax/vqmul/vcrsp and 2 ops
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2019-04-02 23:45:02 +02:00 |
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Unknown W. Brackets
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5414c12a15
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interp: Cleanup prefix/size in vcrsp/vqmul.
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2019-04-02 07:12:34 -07:00 |
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Unknown W. Brackets
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58573cd4b4
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interp: Handle invalid swizzle for vmin/vmax.
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2019-04-02 07:08:33 -07:00 |
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Unknown W. Brackets
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e8c060bb5f
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interp: Correct vwbn and vlgb size behavior.
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2019-04-02 07:08:20 -07:00 |
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Unknown W. Brackets
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89dbfd7d5b
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interp: Better prefixes for vdiv/similar ops.
Turns out it does work, just uses the wrong slot like S/T after all.
These other ops must go through the a similar process.
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2019-04-02 07:07:53 -07:00 |
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Henrik Rydgård
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24cfad87d1
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Merge pull request #11955 from unknownbrackets/vfpu-chunk6
Correct prefixes for several swizzled ops, use zero for invalid
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2019-04-01 17:13:34 +02:00 |
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Henrik Rydgård
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b346142df8
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Merge pull request #11954 from unknownbrackets/vfpu-chunk5
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
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2019-04-01 17:12:03 +02:00 |
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Henrik Rydgård
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3eaead8af1
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Merge pull request #11956 from unknownbrackets/vfpu-chunk7
Correct vmfvc/vmtvc decoding, prefixes on vsgn, vdot, vhdp, and matrix init
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2019-04-01 17:09:46 +02:00 |
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Henrik Rydgård
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8434ac037c
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Merge pull request #11952 from unknownbrackets/vfpu-chunk4
Fix vmfvc, vfim -nan, and improve size/swizzle on vh2f/vf2h/vrnds/vdiv
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2019-04-01 14:14:28 +02:00 |
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Unknown W. Brackets
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6f87987e7b
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interp: Correct prefixes on vdot/vhdp.
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2019-03-31 17:12:21 -07:00 |
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Unknown W. Brackets
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b24f84d1a2
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interp: Handle prefixes on matrix init ops.
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2019-03-31 17:11:24 -07:00 |
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Unknown W. Brackets
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59905de719
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interp: Correct vsgn out of swizzle bounds.
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2019-03-31 17:10:51 -07:00 |
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Unknown W. Brackets
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85ff32eed1
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interp: Handle vsgn prefixing.
One could compare against 3 using this, it just generates zeros to compare
with.
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2019-03-31 17:10:51 -07:00 |
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Unknown W. Brackets
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a5214d0b1a
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Jit: Ignore high bit in vmfvc/vmtvc.
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2019-03-31 17:09:55 -07:00 |
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Unknown W. Brackets
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b881a689c4
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interp: Ignore high bit in vmfvc/vmtvc.
Both 0 and 128 read/write the S prefix, for example.
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2019-03-31 17:09:55 -07:00 |
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Unknown W. Brackets
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dffa238611
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interp: Handle invalid swizzle in vsge/vslt.
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2019-03-31 15:05:43 -07:00 |
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Unknown W. Brackets
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dfd8094f21
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interp: Implement vcrs prefixes and sizes.
It only makes sense as triple, but it can be used as quad/single/etc. and
has consistent and sane results.
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2019-03-31 15:05:15 -07:00 |
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Unknown W. Brackets
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fa7ac7bc64
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interp: Correct simple vmov variant prefixing.
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2019-03-31 15:01:28 -07:00 |
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Unknown W. Brackets
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01aebe54b9
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interp: Correct vdet prefix handling.
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2019-03-31 15:01:11 -07:00 |
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Unknown W. Brackets
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cc58d0d3a3
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interp: Correct prefixes in vsrt ops.
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2019-03-31 15:00:12 -07:00 |
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Unknown W. Brackets
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f2be0cb083
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interp: Correct prefixes for vsbn/vsbz.
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2019-03-31 13:52:59 -07:00 |
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Unknown W. Brackets
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175ceef583
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interp: Cleanup vsocp size handling.
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2019-03-31 13:52:07 -07:00 |
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Unknown W. Brackets
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4a2f8a74dc
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interp: Correct size handling for vi2x ops.
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2019-03-31 13:51:12 -07:00 |
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Unknown W. Brackets
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b75690787e
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interp: Correct swizzle on vx2i ops.
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2019-03-31 13:51:12 -07:00 |
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Unknown W. Brackets
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68cdcba6c5
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interp: Don't write lane 2 on single colorconv.
Not that it's valid to use the op with that size anyway.
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2019-03-31 13:51:12 -07:00 |
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Unknown W. Brackets
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5736b1be2a
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interp: Correct some negative invalid zero cases.
In these cases, the input value wires to +0. Also, transposed the values
in a comment (oops.)
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2019-03-31 13:45:37 -07:00 |
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Unknown W. Brackets
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aa998b815c
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interp: Force vscmp result of invalid to zero.
Some other ops do this, but mostly only that do plus or minus.
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2019-03-31 13:41:48 -07:00 |
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Unknown W. Brackets
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c7e83cd4fa
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interp: Correct vfim for -inf and similar.
Was dropping the sign bit before for inf and nan.
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2019-03-31 13:41:48 -07:00 |
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Unknown W. Brackets
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5749ae09d0
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interp: Correct vmfvc register behavior.
The target and source registers were completely wrong.
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2019-03-31 13:41:48 -07:00 |
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