mirror of
https://github.com/hrydgard/ppsspp.git
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427 lines
10 KiB
C++
427 lines
10 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// WARNING - THIS LIBRARY IS NOT THREAD SAFE!!!
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#ifndef _DOLPHIN_FAKE_CODEGEN_
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#define _DOLPHIN_FAKE_CODEGEN_
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#include <vector>
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#include <stdint.h>
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#include "Common.h"
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#include "Common/CodeBlock.h"
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// VCVT flags
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#define TO_FLOAT 0
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#define TO_INT 1 << 0
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#define IS_SIGNED 1 << 1
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#define ROUND_TO_ZERO 1 << 2
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namespace FakeGen
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{
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enum FakeReg
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{
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// GPRs
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R0 = 0, R1, R2, R3, R4, R5,
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R6, R7, R8, R9, R10, R11,
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// SPRs
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// R13 - R15 are SP, LR, and PC.
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// Almost always referred to by name instead of register number
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R12 = 12, R13 = 13, R14 = 14, R15 = 15,
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R_IP = 12, R_SP = 13, R_LR = 14, R_PC = 15,
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// VFP single precision registers
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S0, S1, S2, S3, S4, S5, S6,
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S7, S8, S9, S10, S11, S12, S13,
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S14, S15, S16, S17, S18, S19, S20,
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S21, S22, S23, S24, S25, S26, S27,
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S28, S29, S30, S31,
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// VFP Double Precision registers
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D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31,
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// ASIMD Quad-Word registers
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Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15,
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// for NEON VLD/VST instructions
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REG_UPDATE = R13,
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INVALID_REG = 0xFFFFFFFF
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};
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enum CCFlags
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{
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CC_EQ = 0, // Equal
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CC_NEQ, // Not equal
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CC_CS, // Carry Set
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CC_CC, // Carry Clear
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CC_MI, // Minus (Negative)
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CC_PL, // Plus
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CC_VS, // Overflow
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CC_VC, // No Overflow
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CC_HI, // Unsigned higher
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CC_LS, // Unsigned lower or same
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CC_GE, // Signed greater than or equal
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CC_LT, // Signed less than
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CC_GT, // Signed greater than
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CC_LE, // Signed less than or equal
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CC_AL, // Always (unconditional) 14
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CC_HS = CC_CS, // Alias of CC_CS Unsigned higher or same
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CC_LO = CC_CC, // Alias of CC_CC Unsigned lower
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};
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const u32 NO_COND = 0xE0000000;
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enum ShiftType
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{
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ST_LSL = 0,
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ST_ASL = 0,
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ST_LSR = 1,
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ST_ASR = 2,
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ST_ROR = 3,
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ST_RRX = 4
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};
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enum IntegerSize
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{
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I_I8 = 0,
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I_I16,
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I_I32,
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I_I64
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};
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enum
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{
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NUMGPRs = 13,
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};
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class FakeXEmitter;
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enum OpType
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{
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TYPE_IMM = 0,
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TYPE_REG,
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TYPE_IMMSREG,
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TYPE_RSR,
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TYPE_MEM
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};
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// This is no longer a proper operand2 class. Need to split up.
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class Operand2
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{
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friend class FakeXEmitter;
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protected:
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u32 Value;
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private:
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OpType Type;
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// IMM types
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u8 Rotation; // Only for u8 values
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// Register types
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u8 IndexOrShift;
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ShiftType Shift;
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public:
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OpType GetType()
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{
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return Type;
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}
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Operand2() {}
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Operand2(u32 imm, OpType type = TYPE_IMM)
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{
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Type = type;
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Value = imm;
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Rotation = 0;
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}
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Operand2(FakeReg Reg)
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{
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Type = TYPE_REG;
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Value = Reg;
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Rotation = 0;
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}
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Operand2(u8 imm, u8 rotation)
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{
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Type = TYPE_IMM;
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Value = imm;
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Rotation = rotation;
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}
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Operand2(FakeReg base, ShiftType type, FakeReg shift) // RSR
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{
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Type = TYPE_RSR;
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_assert_msg_(type != ST_RRX, "Invalid Operand2: RRX does not take a register shift amount");
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IndexOrShift = shift;
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Shift = type;
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Value = base;
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}
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Operand2(FakeReg base, ShiftType type, u8 shift)// For IMM shifted register
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{
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if(shift == 32) shift = 0;
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switch (type)
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{
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case ST_LSL:
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_assert_msg_(shift < 32, "Invalid Operand2: LSL %u", shift);
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break;
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case ST_LSR:
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_assert_msg_(shift <= 32, "Invalid Operand2: LSR %u", shift);
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if (!shift)
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type = ST_LSL;
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if (shift == 32)
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shift = 0;
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break;
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case ST_ASR:
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_assert_msg_(shift < 32, "Invalid Operand2: ASR %u", shift);
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if (!shift)
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type = ST_LSL;
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if (shift == 32)
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shift = 0;
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break;
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case ST_ROR:
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_assert_msg_(shift < 32, "Invalid Operand2: ROR %u", shift);
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if (!shift)
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type = ST_LSL;
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break;
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case ST_RRX:
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_assert_msg_(shift == 0, "Invalid Operand2: RRX does not take an immediate shift amount");
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type = ST_ROR;
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break;
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}
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IndexOrShift = shift;
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Shift = type;
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Value = base;
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Type = TYPE_IMMSREG;
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}
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u32 GetData()
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{
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switch(Type)
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{
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case TYPE_IMM:
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return Imm12Mod(); // This'll need to be changed later
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case TYPE_REG:
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return Rm();
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case TYPE_IMMSREG:
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return IMMSR();
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case TYPE_RSR:
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return RSR();
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default:
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_assert_msg_(false, "GetData with Invalid Type");
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return 0;
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}
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}
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u32 IMMSR() // IMM shifted register
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{
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_assert_msg_(Type == TYPE_IMMSREG, "IMMSR must be imm shifted register");
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return ((IndexOrShift & 0x1f) << 7 | (Shift << 5) | Value);
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}
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u32 RSR() // Register shifted register
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{
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_assert_msg_(Type == TYPE_RSR, "RSR must be RSR Of Course");
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return (IndexOrShift << 8) | (Shift << 5) | 0x10 | Value;
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}
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u32 Rm()
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{
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_assert_msg_(Type == TYPE_REG, "Rm must be with Reg");
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return Value;
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}
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u32 Imm5()
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{
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_assert_msg_(Type == TYPE_IMM, "Imm5 not IMM value");
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return ((Value & 0x0000001F) << 7);
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}
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u32 Imm8()
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{
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_assert_msg_(Type == TYPE_IMM, "Imm8Rot not IMM value");
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return Value & 0xFF;
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}
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u32 Imm8Rot() // IMM8 with Rotation
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{
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_assert_msg_(Type == TYPE_IMM, "Imm8Rot not IMM value");
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_assert_msg_((Rotation & 0xE1) != 0, "Invalid Operand2: immediate rotation %u", Rotation);
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return (1 << 25) | (Rotation << 7) | (Value & 0x000000FF);
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}
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u32 Imm12()
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{
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_assert_msg_(Type == TYPE_IMM, "Imm12 not IMM");
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return (Value & 0x00000FFF);
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}
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u32 Imm12Mod()
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{
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// This is an IMM12 with the top four bits being rotation and the
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// bottom eight being an IMM. This is for instructions that need to
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// expand a 8bit IMM to a 32bit value and gives you some rotation as
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// well.
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// Each rotation rotates to the right by 2 bits
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_assert_msg_(Type == TYPE_IMM, "Imm12Mod not IMM");
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return ((Rotation & 0xF) << 8) | (Value & 0xFF);
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}
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u32 Imm16()
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{
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_assert_msg_(Type == TYPE_IMM, "Imm16 not IMM");
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return ( (Value & 0xF000) << 4) | (Value & 0x0FFF);
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}
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u32 Imm16Low()
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{
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return Imm16();
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}
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u32 Imm16High() // Returns high 16bits
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{
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_assert_msg_(Type == TYPE_IMM, "Imm16 not IMM");
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return ( ((Value >> 16) & 0xF000) << 4) | ((Value >> 16) & 0x0FFF);
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}
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u32 Imm24()
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{
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_assert_msg_(Type == TYPE_IMM, "Imm16 not IMM");
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return (Value & 0x0FFFFFFF);
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}
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};
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// Use these when you don't know if an imm can be represented as an operand2.
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// This lets you generate both an optimal and a fallback solution by checking
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// the return value, which will be false if these fail to find a Operand2 that
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// represents your 32-bit imm value.
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bool TryMakeOperand2(u32 imm, Operand2 &op2);
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bool TryMakeOperand2_AllowInverse(u32 imm, Operand2 &op2, bool *inverse);
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bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated);
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// Use this only when you know imm can be made into an Operand2.
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Operand2 AssumeMakeOperand2(u32 imm);
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inline Operand2 R(FakeReg Reg) { return Operand2(Reg, TYPE_REG); }
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inline Operand2 IMM(u32 Imm) { return Operand2(Imm, TYPE_IMM); }
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inline Operand2 Mem(void *ptr) { return Operand2((u32)(uintptr_t)ptr, TYPE_IMM); }
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//usage: struct {int e;} s; STRUCT_OFFSET(s,e)
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#define STRUCT_OFF(str,elem) ((u32)((u32)&(str).elem-(u32)&(str)))
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struct FixupBranch
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{
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u8 *ptr;
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u32 condition; // Remembers our codition at the time
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int type; //0 = B 1 = BL
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};
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typedef const u8* JumpTarget;
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// XXX: Stop polluting the global namespace
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const u32 I_8 = (1 << 0);
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const u32 I_16 = (1 << 1);
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const u32 I_32 = (1 << 2);
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const u32 I_64 = (1 << 3);
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const u32 I_SIGNED = (1 << 4);
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const u32 I_UNSIGNED = (1 << 5);
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const u32 F_32 = (1 << 6);
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const u32 I_POLYNOMIAL = (1 << 7); // Only used in VMUL/VMULL
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u32 EncodeVd(FakeReg Vd);
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u32 EncodeVn(FakeReg Vn);
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u32 EncodeVm(FakeReg Vm);
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u32 encodedSize(u32 value);
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// Subtracts the base from the register to give us the real one
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FakeReg SubBase(FakeReg Reg);
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// See A.7.1 in the Fakev7-A
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// VMUL F32 scalars can only be up to D15[0], D15[1] - higher scalars cannot be individually addressed
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FakeReg DScalar(FakeReg dreg, int subScalar);
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FakeReg QScalar(FakeReg qreg, int subScalar);
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enum NEONAlignment {
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ALIGN_NONE = 0,
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ALIGN_64 = 1,
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ALIGN_128 = 2,
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ALIGN_256 = 3
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};
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class NEONXEmitter;
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class FakeXEmitter
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{
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friend struct OpArg; // for Write8 etc
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private:
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u8 *code, *startcode;
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u8 *lastCacheFlushEnd;
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u32 condition;
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protected:
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inline void Write32(u32 value) {*(u32*)code = value; code+=4;}
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public:
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FakeXEmitter() : code(0), startcode(0), lastCacheFlushEnd(0) {
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condition = CC_AL << 28;
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}
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FakeXEmitter(u8 *code_ptr) {
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code = code_ptr;
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lastCacheFlushEnd = code_ptr;
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startcode = code_ptr;
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condition = CC_AL << 28;
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}
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virtual ~FakeXEmitter() {}
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void SetCodePointer(u8 *ptr, u8 *writePtr) {}
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const u8 *GetCodePointer() const { return nullptr; }
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void SetCodePtr(u8 *ptr) {}
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void ReserveCodeSpace(u32 bytes) {}
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const u8 *AlignCode16() { return nullptr; }
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const u8 *AlignCodePage() { return nullptr; }
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const u8 *GetCodePtr() const { return nullptr; }
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void FlushIcache() {}
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void FlushIcacheSection(u8 *start, u8 *end) {}
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u8 *GetWritableCodePtr() { return nullptr; }
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CCFlags GetCC() { return CCFlags(condition >> 28); }
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void SetCC(CCFlags cond = CC_AL) {}
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// Special purpose instructions
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// Do nothing
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void NOP(int count = 1) {} //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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#ifdef CALL
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#undef CALL
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#endif
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void QuickCallFunction(FakeReg scratchreg, const void *func);
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template <typename T> void QuickCallFunction(FakeReg scratchreg, T func) {
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QuickCallFunction(scratchreg, (const void *)func);
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}
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}; // class FakeXEmitter
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// Everything that needs to generate machine code should inherit from this.
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// You get memory management for free, plus, you can use all the MOV etc functions without
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// having to prefix them with gen-> or something similar.
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class FakeXCodeBlock : public CodeBlock<FakeXEmitter> {
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public:
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void PoisonMemory(int offset) override {
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}
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};
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} // namespace
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#endif // _DOLPHIN_FAKE_CODEGEN_
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