mirror of
https://github.com/hrydgard/ppsspp.git
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478 lines
14 KiB
C++
478 lines
14 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// WARNING - THIS LIBRARY IS NOT THREAD SAFE!!!
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#ifndef _DOLPHIN_ARM_CODEGEN_
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#define _DOLPHIN_ARM_CODEGEN_
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#include "Common.h"
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#include "MemoryUtil.h"
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#ifndef _M_ARM32
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#error Compile this on ARM.
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#endif
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namespace ArmGen
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{
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enum ARMReg
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{
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// GPRs
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R0 = 0, R1, R2, R3, R4, R5,
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R6, R7, R8, R9, R10, R11,
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// SPRs
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// R13 - R15 are SP, LR, and PC.
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// Almost always referred to by name instead of register number
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R12 = 12, R13 = 13, R14 = 14, R15 = 15,
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_IP = 12, _SP = 13, _LR = 14, _PC = 15,
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// VFP single precision registers
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S0 = 0, S1, S2, S3, S4, S5, S6,
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S7, S8, S9, S10, S11, S12, S13,
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S14, S15, S16, S17, S18, S19, S20,
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S21, S22, S23, S24, S25, S26, S27,
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S28, S29, S30, S31,
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// VFP Double Precision registers
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D0 = 0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31,
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INVALID_REG = 0xFFFFFFFF
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};
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enum CCFlags
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{
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CC_EQ = 0, // Equal
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CC_NEQ, // Not equal
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CC_CS, // Carry Set
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CC_CC, // Carry Clear
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CC_MI, // Minus
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CC_PL, // Plus
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CC_VS, // Overflow
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CC_VC, // No Overflow
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CC_HI, // Unsigned higher
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CC_LS, // Unsigned lower or same
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CC_GE, // Signed greater than or equal
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CC_LT, // Signed less than
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CC_GT, // Signed greater than
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CC_LE, // Signed less than or equal
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CC_AL, // Always (unconditional) 14
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CC_HS = CC_CS, // Higher or same
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CC_LO = CC_CC, // Unsigned Lower
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};
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const u32 NO_COND = 0xE0000000;
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enum ShiftType
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{
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LSL = 0,
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ASL = 0,
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LSR = 1,
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ASR = 2,
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ROR = 3,
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RRX = 4
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};
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enum
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{
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NUMGPRs = 13,
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};
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class ARMXEmitter;
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enum OpType
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{
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TYPE_IMM = 0,
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TYPE_MEM,
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TYPE_REG
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};
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class Operand2
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{
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private:
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OpType Type;
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// IMM types
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u32 Value;
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u8 Rotation; // Only for u8 values
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// Memory types
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bool Away;
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// Register types
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ARMReg Base;
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ARMReg IndexOrShift;
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ShiftType Shift;
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public:
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Operand2() {}
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Operand2(u32 imm, OpType type = TYPE_IMM, bool away = false )
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{
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Type = type;
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Value = imm;
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Away = away;
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}
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Operand2(u8 imm, u8 rotation)
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{
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Type = TYPE_IMM;
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Value = imm;
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Rotation = rotation;
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}
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Operand2(ARMReg base, ShiftType type, ARMReg shift)
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{
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Type = TYPE_REG;
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_assert_msg_(DYNA_REC, type != RRX, "Invalid Operand2: RRX does not take a register shift amount");
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IndexOrShift = shift;
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Shift = type;
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Base = base;
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}
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Operand2(ARMReg base)
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{
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_assert_msg_(DYNA_REC, false, "Can't have just register operand...yet");
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}
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const u32 RSR() // Register shifted register
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{
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_assert_msg_(DYNA_REC, !(Type == TYPE_IMM), "RSR can't be IMM");
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return (IndexOrShift << 8) | (Shift << 5) | 0x10 | Base;
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}
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const u32 Imm8Rot() // IMM8 with Rotation
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8Rot not IMM value;");
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_assert_msg_(DYNA_REC, (Rotation & 0xE1) != 0, "Invalid Operand2: immediate rotation %u", Rotation);
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return (1 << 25) | (Rotation << 7) | (Value & 0x000000FF);
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}
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const u32 Imm12()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm12 not IMM");
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return (Value & 0x00000FFF);
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}
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const u32 Imm12Mod()
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{
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// This is a IMM12 with the top four bits being rotation and the
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// bottom eight being a IMM. This is for instructions that need to
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// expand a 8bit IMM to a 32bit value and gives you some rotation as
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// well.
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// 0000 = no rotation
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// 0001 = Rotate right 2 bits
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// 0010 = Rotate right 4 bits
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// 0011 = Rotate right 6 bits
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// 0100 = Rotate right 8 bits (So the IMM is in the top 8 bits of the IMM32)
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// See A5.2.4 in the Arm reference manual for more.
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm12Mod not IMM");
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return ((Rotation & 0xF) << 8) | (Value & 0xFF);
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}
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const u32 Imm16()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
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return ( (Value & 0xF000) << 4) | (Value & 0x0FFF);
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}
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const u32 Imm16Low()
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{
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return Imm16();
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}
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const u32 Imm16High() // Returns high 16bits
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
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return ( ((Value >> 16) & 0xF000) << 4) | ((Value >> 16) & 0x0FFF);
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}
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const u32 Imm24()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
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return (Value & 0x0FFFFFFF);
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}
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/*Operand2(ARMReg base, ShiftType type = LSL, u8 shift = 0)
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{
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switch (type)
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{
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case LSL:
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_assert_msg_(DYNA_REC, shift >= 32, "Invalid Operand2: LSL %u", shift);
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break;
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case LSR:
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_assert_msg_(DYNA_REC, shift > 32, "Invalid Operand2: LSR %u", shift);
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if (!shift)
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type = LSL;
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if (shift == 32)
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shift = 0;
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break;
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case ASR:
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_assert_msg_(DYNA_REC, shift > 32, "Invalid Operand2: LSR %u", shift);
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if (!shift)
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type = LSL;
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if (shift == 32)
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shift = 0;
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break;
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case ROR:
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_assert_msg_(DYNA_REC, shift >= 32, "Invalid Operand2: ROR %u", shift);
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if (!shift)
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type = LSL;
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break;
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case RRX:
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_assert_msg_(DYNA_REC, shift != 0, "Invalid Operand2: RRX does not take an immediate shift amount");
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type = ROR;
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break;
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}
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encoding = (shift << 7) | (type << 5) | base;
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} */
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};
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inline Operand2 Mem(void *ptr) { return Operand2((u32)ptr, true); }
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//usage: int a[]; ARRAY_OFFSET(a,10)
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#define ARRAY_OFFSET(array,index) ((u32)((u64)&(array)[index]-(u64)&(array)[0]))
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//usage: struct {int e;} s; STRUCT_OFFSET(s,e)
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#define STRUCT_OFFSET(str,elem) ((u32)((u64)&(str).elem-(u64)&(str)))
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struct FixupBranch
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{
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u8 *ptr;
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u32 condition; // Remembers our codition at the time
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int type; //0 = B 1 = BL
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};
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typedef const u8* JumpTarget;
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class ARMXEmitter
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{
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friend struct OpArg; // for Write8 etc
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private:
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u8 *code, *startcode;
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u32 condition;
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void WriteDataOp(u32 op, ARMReg dest, ARMReg src, Operand2 op2);
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void WriteDataOp(u32 op, ARMReg dest, ARMReg src, ARMReg op2);
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void WriteDataOp(u32 op, ARMReg dest, ARMReg src);
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void WriteMoveOp(u32 op, ARMReg dest, Operand2 op2, bool TopBits = false);
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void WriteStoreOp(u32 op, ARMReg dest, ARMReg src, Operand2 op2);
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void WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList);
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protected:
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inline void Write32(u32 value) {*(u32*)code = value; code+=4;}
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public:
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ARMXEmitter() { code = NULL; startcode = NULL; condition = CC_AL << 28;}
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ARMXEmitter(u8 *code_ptr) { code = code_ptr; startcode = code_ptr; condition = CC_AL << 28;}
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virtual ~ARMXEmitter() {}
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void SetCodePtr(u8 *ptr);
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void ReserveCodeSpace(u32 bytes);
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr() const;
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void Flush();
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u8 *GetWritableCodePtr();
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void SetCC(CCFlags cond = CC_AL);
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// Debug Breakpoint
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void BKPT(u16 arg);
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// Hint instruction
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void YIELD();
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// Do nothing
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void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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#ifdef CALL
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#undef CALL
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#endif
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void B (Operand2 op2);
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FixupBranch B();
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void BL(const void *ptr);
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FixupBranch BL();
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void BLX(ARMReg src);
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void BX (ARMReg src);
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void SetJumpTarget(FixupBranch const &branch);
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void PUSH(const int num, ...);
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void POP(const int num, ...);
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// Data operations
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void AND (ARMReg dest, ARMReg src, Operand2 op2);
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void ANDS(ARMReg dest, ARMReg src, Operand2 op2);
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void AND (ARMReg dest, ARMReg src, ARMReg op2);
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void ANDS(ARMReg dest, ARMReg src, ARMReg op2);
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void EOR (ARMReg dest, ARMReg src, Operand2 op2);
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void EORS(ARMReg dest, ARMReg src, Operand2 op2);
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void EOR (ARMReg dest, ARMReg src, ARMReg op2);
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void EORS(ARMReg dest, ARMReg src, ARMReg op2);
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void SUB (ARMReg dest, ARMReg src, Operand2 op2);
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void SUBS(ARMReg dest, ARMReg src, Operand2 op2);
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void SUB (ARMReg dest, ARMReg src, ARMReg op2);
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void SUBS(ARMReg dest, ARMReg src, ARMReg op2);
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void RSB (ARMReg dest, ARMReg src, Operand2 op2);
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void RSBS(ARMReg dest, ARMReg src, Operand2 op2);
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void RSB (ARMReg dest, ARMReg src, ARMReg op2);
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void RSBS(ARMReg dest, ARMReg src, ARMReg op2);
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void ADD (ARMReg dest, ARMReg src, Operand2 op2);
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void ADDS(ARMReg dest, ARMReg src, Operand2 op2);
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void ADD (ARMReg dest, ARMReg src, ARMReg op2);
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void ADDS(ARMReg dest, ARMReg src, ARMReg op2);
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void ADC (ARMReg dest, ARMReg src, Operand2 op2);
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void ADCS(ARMReg dest, ARMReg src, Operand2 op2);
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void ADC (ARMReg dest, ARMReg src, ARMReg op2);
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void ADCS(ARMReg dest, ARMReg src, ARMReg op2);
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void SBC (ARMReg dest, ARMReg src, Operand2 op2);
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void SBCS(ARMReg dest, ARMReg src, Operand2 op2);
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void SBC (ARMReg dest, ARMReg src, ARMReg op2);
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void SBCS(ARMReg dest, ARMReg src, ARMReg op2);
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void REV (ARMReg dest, ARMReg src );
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void RSC (ARMReg dest, ARMReg src, Operand2 op2);
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void RSCS(ARMReg dest, ARMReg src, Operand2 op2);
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void RSC (ARMReg dest, ARMReg src, ARMReg op2);
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void RSCS(ARMReg dest, ARMReg src, ARMReg op2);
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void TST ( ARMReg src, Operand2 op2);
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void TST ( ARMReg src, ARMReg op2);
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void TEQ ( ARMReg src, Operand2 op2);
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void TEQ ( ARMReg src, ARMReg op2);
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void CMP ( ARMReg src, Operand2 op2);
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void CMP ( ARMReg src, ARMReg op2);
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void CMN ( ARMReg src, Operand2 op2);
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void CMN ( ARMReg src, ARMReg op2);
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void ORR (ARMReg dest, ARMReg src, Operand2 op2);
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void ORRS(ARMReg dest, ARMReg src, Operand2 op2);
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void ORR (ARMReg dest, ARMReg src, ARMReg op2);
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void ORRS(ARMReg dest, ARMReg src, ARMReg op2);
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void MOV (ARMReg dest, Operand2 op2);
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void MOVS(ARMReg dest, Operand2 op2);
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void MOV (ARMReg dest, ARMReg src );
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void MOVS(ARMReg dest, ARMReg src );
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void BIC (ARMReg dest, ARMReg src, Operand2 op2);
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void BICS(ARMReg dest, ARMReg src, Operand2 op2);
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void BIC (ARMReg dest, ARMReg src, ARMReg op2);
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void BICS(ARMReg dest, ARMReg src, ARMReg op2);
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void MVN (ARMReg dest, Operand2 op2);
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void MVNS(ARMReg dest, Operand2 op2);
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void MVN (ARMReg dest, ARMReg op2);
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void MVNS(ARMReg dest, ARMReg op2);
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// Using just MSR here messes with our defines on the PPC side of stuff
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// Just need to put an underscore here, bit annoying.
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void _MSR (bool nzcvq, bool g, Operand2 op2);
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void _MSR (bool nzcvq, bool g, ARMReg src );
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void MRS (ARMReg dest);
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// Memory load/store operations
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void MOVT(ARMReg dest, Operand2 op2, bool TopBits = false);
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void MOVW(ARMReg dest, Operand2 op2);
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void LDR (ARMReg dest, ARMReg src, Operand2 op2);
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void LDR (ARMReg dest, ARMReg base, ARMReg offset = R0, bool Index = false, bool Add = false);
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void LDRB(ARMReg dest, ARMReg src, Operand2 op2);
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void STR (ARMReg dest, ARMReg src, Operand2 op2);
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void STR (ARMReg dest, ARMReg base, ARMReg offset = R0, bool Index = false, bool Add = false);
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void STRB(ARMReg dest, ARMReg src, Operand2 op2);
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void STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
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void LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
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// Utility functions
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// The difference between this and CALL is that this aligns the stack
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// where appropriate.
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void ARMABI_CallFunction(void *func);
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void ARMABI_PushAllCalleeSavedRegsAndAdjustStack();
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void ARMABI_PopAllCalleeSavedRegsAndAdjustStack();
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void ARMABI_MOVIMM32(ARMReg reg, u32 val);
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void ARMABI_MOVIMM32(Operand2 op, u32 val);
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void UpdateAPSR(bool NZCVQ, u8 Flags, bool GE, u8 GEval);
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// Strange call wrappers.
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void CallCdeclFunction3(void* fnptr, u32 arg0, u32 arg1, u32 arg2);
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void CallCdeclFunction4(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3);
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void CallCdeclFunction5(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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void CallCdeclFunction6(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5);
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#define CallCdeclFunction3_I(a,b,c,d) CallCdeclFunction3((void *)(a), (b), (c), (d))
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#define CallCdeclFunction4_I(a,b,c,d,e) CallCdeclFunction4((void *)(a), (b), (c), (d), (e))
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#define CallCdeclFunction5_I(a,b,c,d,e,f) CallCdeclFunction5((void *)(a), (b), (c), (d), (e), (f))
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#define CallCdeclFunction6_I(a,b,c,d,e,f,g) CallCdeclFunction6((void *)(a), (b), (c), (d), (e), (f), (g))
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#define DECLARE_IMPORT(x)
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}; // class ARMXEmitter
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// Everything that needs to generate X86 code should inherit from this.
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// You get memory management for free, plus, you can use all the MOV etc functions without
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// having to prefix them with gen-> or something similar.
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class ARMXCodeBlock : public ARMXEmitter
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{
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protected:
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u8 *region;
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size_t region_size;
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public:
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ARMXCodeBlock() : region(NULL), region_size(0) {}
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virtual ~ARMXCodeBlock() { if (region) FreeCodeSpace(); }
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// Call this before you generate any code.
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void AllocCodeSpace(int size)
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{
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region_size = size;
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region = (u8*)AllocateExecutableMemory(region_size);
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SetCodePtr(region);
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}
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// Always clear code space with breakpoints, so that if someone accidentally executes
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// uninitialized, it just breaks into the debugger.
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void ClearCodeSpace()
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{
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// x86/64: 0xCC = breakpoint
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memset(region, 0xCC, region_size);
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ResetCodePtr();
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}
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// Call this when shutting down. Don't rely on the destructor, even though it'll do the job.
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void FreeCodeSpace()
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{
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FreeMemoryPages(region, region_size);
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region = NULL;
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region_size = 0;
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}
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bool IsInCodeSpace(u8 *ptr)
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{
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return ptr >= region && ptr < region + region_size;
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}
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// Cannot currently be undone. Will write protect the entire code region.
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// Start over if you need to change the code (call FreeCodeSpace(), AllocCodeSpace()).
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void WriteProtect()
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{
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WriteProtectMemory(region, region_size, true);
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}
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void ResetCodePtr()
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{
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SetCodePtr(region);
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}
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size_t GetSpaceLeft() const
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{
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return region_size - (GetCodePtr() - region);
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}
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};
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} // namespace
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#endif // _DOLPHIN_INTEL_CODEGEN_
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