mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-12-04 20:06:51 +00:00
473 lines
14 KiB
C++
473 lines
14 KiB
C++
// Copyright (c) 2022- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include <cstdint>
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#include <cstring>
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#include <type_traits>
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#include "Common/CodeBlock.h"
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#include "Common/Common.h"
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namespace RiscVGen {
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enum RiscVReg {
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X0 = 0, X1, X2, X3, X4, X5, X6, X7,
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X8, X9, X10, X11, X12, X13, X14, X15,
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X16, X17, X18, X19, X20, X21, X22, X23,
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X24, X25, X26, X27, X28, X29, X30, X31,
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R_ZERO = 0,
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R_RA = 1,
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R_SP = 2,
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R_GP = 3,
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R_TP = 4,
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R_FP = 8,
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F0 = 0x20, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F24, F25, F26, F27, F28, F29, F30, F31,
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};
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enum class FixupBranchType {
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B,
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J,
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CB,
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CJ,
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};
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enum class Fence {
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I = 0b1000,
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O = 0b0100,
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R = 0b0010,
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W = 0b0001,
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RW = R | W,
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IO = I | O,
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};
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ENUM_CLASS_BITOPS(Fence);
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enum class Atomic {
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NONE = 0b00,
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ACQUIRE = 0b10,
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RELEASE = 0b01,
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SEQUENTIAL = 0b11,
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};
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enum class Round {
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NEAREST_EVEN = 0b000,
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TOZERO = 0b001,
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DOWN = 0b010,
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UP = 0b011,
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NEAREST_MAX = 0b100,
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DYNAMIC = 0b111,
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};
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enum class FConv {
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W = 0x0000,
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WU = 0x0001,
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L = 0x0002,
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LU = 0x0003,
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S = 0x1000,
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D = 0x1001,
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Q = 0x1003,
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};
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enum class FMv {
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X,
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W,
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D,
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};
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enum class Csr {
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FFlags = 0x001,
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FRm = 0x002,
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FCsr = 0x003,
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Cycle = 0xC00,
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Time = 0xC01,
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InstRet = 0xC02,
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CycleH = 0xC80,
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TimeH = 0xC81,
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InstRetH = 0xC82,
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};
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struct FixupBranch {
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FixupBranch() {}
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FixupBranch(const u8 *p, FixupBranchType t) : ptr(p), type(t) {}
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~FixupBranch();
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const u8 *ptr = nullptr;
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FixupBranchType type;
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};
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class RiscVEmitter {
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public:
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RiscVEmitter() {}
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RiscVEmitter(const u8 *codePtr, u8 *writablePtr);
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virtual ~RiscVEmitter() {}
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void SetCodePointer(const u8 *ptr, u8 *writePtr);
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const u8 *GetCodePointer() const;
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u8 *GetWritableCodePtr();
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void ReserveCodeSpace(u32 bytes);
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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void FlushIcache();
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void FlushIcacheSection(const u8 *start, const u8 *end);
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void SetJumpTarget(FixupBranch &branch);
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bool BInRange(const void *func) const;
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bool JInRange(const void *func) const;
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void LUI(RiscVReg rd, s32 simm32);
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void AUIPC(RiscVReg rd, s32 simm32);
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void JAL(RiscVReg rd, const void *dst);
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void JALR(RiscVReg rd, RiscVReg rs1, s32 simm12);
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FixupBranch JAL(RiscVReg rd);
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// Psuedo-instructions for convenience/clarity.
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void J(const void *dst) {
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JAL(R_ZERO, dst);
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}
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void JR(RiscVReg rs1, u32 simm12 = 0) {
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JALR(R_ZERO, rs1, simm12);
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}
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void RET() {
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JR(R_RA);
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}
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FixupBranch J() {
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return JAL(R_ZERO);
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}
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void BEQ(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BNE(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BLT(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BGE(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BLTU(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BGEU(RiscVReg rs1, RiscVReg rs2, const void *dst);
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FixupBranch BEQ(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BNE(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BLT(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BGE(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BLTU(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BGEU(RiscVReg rs1, RiscVReg rs2);
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void LB(RiscVReg rd, RiscVReg addr, s32 simm12);
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void LH(RiscVReg rd, RiscVReg addr, s32 simm12);
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void LW(RiscVReg rd, RiscVReg addr, s32 simm12);
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void LBU(RiscVReg rd, RiscVReg addr, s32 simm12);
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void LHU(RiscVReg rd, RiscVReg addr, s32 simm12);
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void SB(RiscVReg rs2, RiscVReg addr, s32 simm12);
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void SH(RiscVReg rs2, RiscVReg addr, s32 simm12);
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void SW(RiscVReg rs2, RiscVReg addr, s32 simm12);
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void ADDI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SLTI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SLTIU(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void XORI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void ORI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void ANDI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void NOP() {
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ADDI(R_ZERO, R_ZERO, 0);
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}
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void MV(RiscVReg rd, RiscVReg rs1) {
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ADDI(rd, rs1, 0);
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}
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void NOT(RiscVReg rd, RiscVReg rs1) {
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XORI(rd, rs1, -1);
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}
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// The temp reg is only possibly used for 64-bit values.
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template <typename T>
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void LI(RiscVReg rd, const T &v, RiscVReg temp = R_ZERO) {
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_assert_msg_(rd != R_ZERO, "LI to X0");
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_assert_msg_(rd < F0 && temp < F0, "LI to non-GPR");
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uint64_t value = AsImmediate<T, std::is_signed<T>::value>(v);
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SetRegToImmediate(rd, value, temp);
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}
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void SLLI(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRLI(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRAI(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void ADD(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SUB(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLT(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLTU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void XOR(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRA(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void OR(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void AND(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void NEG(RiscVReg rd, RiscVReg rs) {
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SUB(rd, R_ZERO, rs);
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}
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void FENCE(Fence predecessor, Fence successor);
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void FENCE_TSO();
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void ECALL();
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void EBREAK();
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// 64-bit instructions - oens ending in W sign extend result to 32 bits.
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void LWU(RiscVReg rd, RiscVReg addr, s32 simm12);
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void LD(RiscVReg rd, RiscVReg addr, s32 simm12);
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void SD(RiscVReg rs2, RiscVReg addr, s32 simm12);
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void ADDIW(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SLLIW(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRLIW(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRAIW(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void ADDW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SUBW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLLW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRLW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRAW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void NEGW(RiscVReg rd, RiscVReg rs) {
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SUBW(rd, R_ZERO, rs);
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}
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// Integer multiplication and division.
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void MUL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void MULH(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void MULHSU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void MULHU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIV(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIVU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REM(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REMU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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// 64-bit only multiply and divide.
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void MULW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIVW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIVUW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REMW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REMUW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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// Atomic memory operations.
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void LR(int bits, RiscVReg rd, RiscVReg addr, Atomic ordering);
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void SC(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOSWAP(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOADD(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOAND(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOOR(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOXOR(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOMIN(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOMAX(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOMINU(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOMAXU(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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// Floating point (same funcs for single/double/quad, if supported.)
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void FL(int bits, RiscVReg rd, RiscVReg addr, s32 simm12);
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void FS(int bits, RiscVReg rs2, RiscVReg addr, s32 simm12);
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void FLW(RiscVReg rd, RiscVReg addr, s32 simm12) {
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FL(32, rd, addr, simm12);
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}
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void FSW(RiscVReg rs2, RiscVReg addr, s32 simm12) {
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FS(32, rs2, addr, simm12);
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}
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void FMADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
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void FMSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
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void FNMSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
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void FNMADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
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void FADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
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void FSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
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void FMUL(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
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void FDIV(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
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void FSQRT(int bits, RiscVReg rd, RiscVReg rs1, Round rm = Round::DYNAMIC);
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void FSGNJ(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FSGNJN(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FSGNJX(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FMV(int bits, RiscVReg rd, RiscVReg rs) {
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FSGNJ(bits, rd, rs, rs);
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}
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void FNEG(int bits, RiscVReg rd, RiscVReg rs) {
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FSGNJN(bits, rd, rs, rs);
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}
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void FABS(int bits, RiscVReg rd, RiscVReg rs) {
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FSGNJX(bits, rd, rs, rs);
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}
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void FMIN(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FMAX(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FCVT(FConv to, FConv from, RiscVReg rd, RiscVReg rs1, Round rm = Round::DYNAMIC);
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void FMV(FMv to, FMv from, RiscVReg rd, RiscVReg rs1);
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void FEQ(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FLT(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FLE(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FCLASS(int bits, RiscVReg rd, RiscVReg rs1);
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// Control state register manipulation.
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void CSRRW(RiscVReg rd, Csr csr, RiscVReg rs1);
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void CSRRS(RiscVReg rd, Csr csr, RiscVReg rs1);
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void CSRRC(RiscVReg rd, Csr csr, RiscVReg rs1);
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void CSRRWI(RiscVReg rd, Csr csr, u8 uimm5);
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void CSRRSI(RiscVReg rd, Csr csr, u8 uimm5);
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void CSRRCI(RiscVReg rd, Csr csr, u8 uimm5);
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void FRRM(RiscVReg rd) {
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CSRRS(rd, Csr::FRm, R_ZERO);
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}
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void FSRM(RiscVReg rs) {
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CSRRW(R_ZERO, Csr::FRm, rs);
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}
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void FSRMI(RiscVReg rd, Round rm) {
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_assert_msg_(rm != Round::DYNAMIC, "Cannot set FRm to DYNAMIC");
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CSRRWI(rd, Csr::FRm, (uint8_t)rm);
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}
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void FSRMI(Round rm) {
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FSRMI(R_ZERO, rm);
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}
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// Compressed instructions.
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void C_ADDI4SPN(RiscVReg rd, u32 nzuimm10);
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void C_FLD(RiscVReg rd, RiscVReg addr, u8 uimm8);
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void C_LW(RiscVReg rd, RiscVReg addr, u8 uimm7);
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void C_FLW(RiscVReg rd, RiscVReg addr, u8 uimm7);
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void C_LD(RiscVReg rd, RiscVReg addr, u8 uimm8);
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void C_FSD(RiscVReg rs2, RiscVReg addr, u8 uimm8);
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void C_SW(RiscVReg rs2, RiscVReg addr, u8 uimm7);
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void C_FSW(RiscVReg rs2, RiscVReg addr, u8 uimm7);
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void C_SD(RiscVReg rs2, RiscVReg addr, u8 uimm8);
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void C_NOP();
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void C_ADDI(RiscVReg rd, s8 nzsimm6);
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void C_JAL(const void *dst);
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FixupBranch C_JAL();
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void C_ADDIW(RiscVReg rd, s8 simm6);
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void C_LI(RiscVReg rd, s8 simm6);
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void C_ADDI16SP(s32 nzsimm10);
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void C_LUI(RiscVReg rd, s32 nzsimm18);
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void C_SRLI(RiscVReg rd, u8 nzuimm6);
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void C_SRAI(RiscVReg rd, u8 nzuimm6);
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void C_ANDI(RiscVReg rd, s8 simm6);
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void C_SUB(RiscVReg rd, RiscVReg rs2);
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void C_XOR(RiscVReg rd, RiscVReg rs2);
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void C_OR(RiscVReg rd, RiscVReg rs2);
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void C_AND(RiscVReg rd, RiscVReg rs2);
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void C_SUBW(RiscVReg rd, RiscVReg rs2);
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void C_ADDW(RiscVReg rd, RiscVReg rs2);
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void C_J(const void *dst);
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void C_BEQZ(RiscVReg rs1, const void *dst);
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void C_BNEZ(RiscVReg rs1, const void *dst);
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FixupBranch C_J();
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FixupBranch C_BEQZ(RiscVReg rs1);
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FixupBranch C_BNEZ(RiscVReg rs1);
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void C_SLLI(RiscVReg rd, u8 nzuimm6);
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void C_FLDSP(RiscVReg rd, u32 uimm9);
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void C_LWSP(RiscVReg rd, u8 uimm8);
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void C_FLWSP(RiscVReg rd, u8 uimm8);
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void C_LDSP(RiscVReg rd, u32 uimm9);
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void C_JR(RiscVReg rs1);
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|
void C_MV(RiscVReg rd, RiscVReg rs2);
|
|
void C_EBREAK();
|
|
void C_JALR(RiscVReg rs1);
|
|
void C_ADD(RiscVReg rd, RiscVReg rs2);
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|
void C_FSDSP(RiscVReg rs2, u32 uimm9);
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|
void C_SWSP(RiscVReg rs2, u8 uimm8);
|
|
void C_FSWSP(RiscVReg rs2, u8 uimm8);
|
|
void C_SDSP(RiscVReg rs2, u32 uimm9);
|
|
|
|
bool CBInRange(const void *func) const;
|
|
bool CJInRange(const void *func) const;
|
|
|
|
bool SetAutoCompress(bool flag) {
|
|
bool prev = autoCompress_;
|
|
autoCompress_ = flag;
|
|
return prev;
|
|
}
|
|
bool AutoCompress() const;
|
|
|
|
private:
|
|
void SetJumpTarget(FixupBranch &branch, const void *dst);
|
|
bool BInRange(const void *src, const void *dst) const;
|
|
bool JInRange(const void *src, const void *dst) const;
|
|
bool CBInRange(const void *src, const void *dst) const;
|
|
bool CJInRange(const void *src, const void *dst) const;
|
|
|
|
void SetRegToImmediate(RiscVReg rd, uint64_t value, RiscVReg temp);
|
|
|
|
template <typename T, bool extend>
|
|
uint64_t AsImmediate(const T &v) {
|
|
static_assert(std::is_trivial<T>::value, "Immediate argument must be a simple type");
|
|
static_assert(sizeof(T) <= 8, "Immediate argument size should be 8, 16, 32, or 64 bits");
|
|
|
|
// Copy the type to allow floats and avoid endian issues.
|
|
if (sizeof(T) == 8) {
|
|
uint64_t value;
|
|
memcpy(&value, &v, sizeof(value));
|
|
return value;
|
|
} else if (sizeof(T) == 4) {
|
|
uint32_t value;
|
|
memcpy(&value, &v, sizeof(value));
|
|
if (extend)
|
|
return (int64_t)(int32_t)value;
|
|
return value;
|
|
} else if (sizeof(T) == 2) {
|
|
uint16_t value;
|
|
memcpy(&value, &v, sizeof(value));
|
|
if (extend)
|
|
return (int64_t)(int16_t)value;
|
|
return value;
|
|
} else if (sizeof(T) == 1) {
|
|
uint8_t value;
|
|
memcpy(&value, &v, sizeof(value));
|
|
if (extend)
|
|
return (int64_t)(int8_t)value;
|
|
return value;
|
|
}
|
|
return (uint64_t)v;
|
|
}
|
|
|
|
inline void Write32(u32 value) {
|
|
Write16(value & 0x0000FFFF);
|
|
Write16(value >> 16);
|
|
}
|
|
inline void Write16(u16 value) {
|
|
*(u16 *)writable_ = value;
|
|
code_ += 2;
|
|
writable_ += 2;
|
|
}
|
|
|
|
const u8 *code_ = nullptr;
|
|
u8 *writable_ = nullptr;
|
|
const u8 *lastCacheFlushEnd_ = nullptr;
|
|
bool autoCompress_ = false;
|
|
};
|
|
|
|
class MIPSCodeBlock : public CodeBlock<RiscVEmitter> {
|
|
private:
|
|
void PoisonMemory(int offset) override;
|
|
};
|
|
|
|
};
|