mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-12-13 00:17:21 +00:00
321 lines
8.6 KiB
C++
321 lines
8.6 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/x86/Jit.h"
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#include "Core/MIPS/x86/Asm.h"
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#include "Core/MIPS/x86/RegCache.h"
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using namespace Gen;
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static const int allocationOrder[] =
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{
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// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into this.
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// On x64, RCX and RDX are the first args. CallProtectedFunction() assumes they're not regcached.
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#ifdef _M_X64
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#ifdef _WIN32
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RSI, RDI, R13, R14, R8, R9, R10, R11, R12,
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#else
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RBP, R13, R14, R8, R9, R10, R11, R12,
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#endif
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#elif _M_IX86
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ESI, EDI, EBP, EDX, ECX, // Let's try to free up EBX as well.
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#endif
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};
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void GPRRegCache::FlushBeforeCall() {
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// TODO: Only flush the non-preserved-by-callee registers.
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Flush();
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}
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GPRRegCache::GPRRegCache() : mips(0), emit(0) {
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memset(regs, 0, sizeof(regs));
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memset(xregs, 0, sizeof(xregs));
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}
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void GPRRegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
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this->mips = mips;
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for (int i = 0; i < NUM_X_REGS; i++) {
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xregs[i].free = true;
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xregs[i].dirty = false;
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xregs[i].allocLocked = false;
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}
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memset(regs, 0, sizeof(regs));
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OpArg base = GetDefaultLocation(MIPS_REG_ZERO);
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for (int i = 0; i < NUM_MIPS_GPRS; i++) {
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regs[i].location = base;
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base.IncreaseOffset(sizeof(u32));
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}
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// todo: sort to find the most popular regs
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/*
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int maxPreload = 2;
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for (int i = 0; i < NUM_MIPS_GPRS; i++)
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{
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if (stats.numReads[i] > 2 || stats.numWrites[i] >= 2)
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{
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LoadToX64(i, true, false); //stats.firstRead[i] <= stats.firstWrite[i], false);
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maxPreload--;
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if (!maxPreload)
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break;
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}
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}*/
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//Find top regs - preload them (load bursts ain't bad)
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//But only preload IF written OR reads >= 3
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}
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// these are MIPS reg indices
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void GPRRegCache::Lock(MIPSGPReg p1, MIPSGPReg p2, MIPSGPReg p3, MIPSGPReg p4) {
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regs[p1].locked = true;
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if (p2 != MIPS_REG_INVALID) regs[p2].locked = true;
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if (p3 != MIPS_REG_INVALID) regs[p3].locked = true;
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if (p4 != MIPS_REG_INVALID) regs[p4].locked = true;
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}
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// these are x64 reg indices
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void GPRRegCache::LockX(int x1, int x2, int x3, int x4) {
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if (xregs[x1].allocLocked) {
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PanicAlert("RegCache: x %i already locked!", x1);
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}
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xregs[x1].allocLocked = true;
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if (x2 != 0xFF) xregs[x2].allocLocked = true;
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if (x3 != 0xFF) xregs[x3].allocLocked = true;
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if (x4 != 0xFF) xregs[x4].allocLocked = true;
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}
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void GPRRegCache::UnlockAll() {
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for (int i = 0; i < NUM_MIPS_GPRS; i++)
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regs[i].locked = false;
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}
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void GPRRegCache::UnlockAllX() {
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for (int i = 0; i < NUM_X_REGS; i++)
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xregs[i].allocLocked = false;
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}
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X64Reg GPRRegCache::GetFreeXReg()
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{
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int aCount;
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const int *aOrder = GetAllocationOrder(aCount);
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for (int i = 0; i < aCount; i++)
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{
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X64Reg xr = (X64Reg)aOrder[i];
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if (!xregs[xr].allocLocked && xregs[xr].free)
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{
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return (X64Reg)xr;
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}
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}
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//Okay, not found :( Force grab one
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//TODO - add a pass to grab xregs whose mipsreg is not used in the next 3 instructions
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for (int i = 0; i < aCount; i++)
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{
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X64Reg xr = (X64Reg)aOrder[i];
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if (xregs[xr].allocLocked)
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continue;
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MIPSGPReg preg = xregs[xr].mipsReg;
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if (!regs[preg].locked)
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{
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StoreFromRegister(preg);
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return xr;
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}
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}
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//Still no dice? Die!
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_assert_msg_(JIT, 0, "Regcache ran out of regs");
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return (X64Reg) -1;
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}
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void GPRRegCache::FlushR(X64Reg reg)
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{
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if (reg >= NUM_X_REGS)
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PanicAlert("Flushing non existent reg");
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else if (!xregs[reg].free)
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StoreFromRegister(xregs[reg].mipsReg);
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}
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int GPRRegCache::SanityCheck() const {
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for (int i = 0; i < NUM_MIPS_GPRS; i++) {
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const MIPSGPReg r = MIPSGPReg(i);
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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Gen::X64Reg simple = regs[i].location.GetSimpleReg();
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if (xregs[simple].allocLocked)
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return 1;
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if (xregs[simple].mipsReg != r)
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return 2;
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}
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else if (regs[i].location.IsImm())
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return 3;
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}
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}
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return 0;
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}
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void GPRRegCache::DiscardRegContentsIfCached(MIPSGPReg preg) {
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if (regs[preg].away && regs[preg].location.IsSimpleReg()) {
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X64Reg xr = regs[preg].location.GetSimpleReg();
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xregs[xr].free = true;
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xregs[xr].dirty = false;
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xregs[xr].mipsReg = MIPS_REG_INVALID;
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regs[preg].away = false;
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regs[preg].location = GetDefaultLocation(preg);
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}
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}
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void GPRRegCache::SetImm(MIPSGPReg preg, u32 immValue) {
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// ZERO is always zero. Let's just make sure.
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if (preg == MIPS_REG_ZERO)
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immValue = 0;
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DiscardRegContentsIfCached(preg);
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regs[preg].away = true;
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regs[preg].location = Imm32(immValue);
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}
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bool GPRRegCache::IsImm(MIPSGPReg preg) const {
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// Always say yes for ZERO, even if it's in a temp reg.
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if (preg == MIPS_REG_ZERO)
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return true;
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return regs[preg].location.IsImm();
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}
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u32 GPRRegCache::GetImm(MIPSGPReg preg) const {
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_dbg_assert_msg_(JIT, IsImm(preg), "Reg %d must be an immediate.", preg);
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// Always 0 for ZERO.
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if (preg == MIPS_REG_ZERO)
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return 0;
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return regs[preg].location.GetImmValue();
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}
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const int *GPRRegCache::GetAllocationOrder(int &count) {
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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OpArg GPRRegCache::GetDefaultLocation(MIPSGPReg reg) const {
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return M(&mips->r[reg]);
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}
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void GPRRegCache::KillImmediate(MIPSGPReg preg, bool doLoad, bool makeDirty) {
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if (regs[preg].away) {
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if (regs[preg].location.IsImm())
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MapReg(preg, doLoad, makeDirty);
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else if (regs[preg].location.IsSimpleReg())
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xregs[RX(preg)].dirty |= makeDirty;
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}
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}
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void GPRRegCache::MapReg(MIPSGPReg i, bool doLoad, bool makeDirty) {
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if (!regs[i].away && regs[i].location.IsImm())
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PanicAlert("Bad immediate");
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if (!regs[i].away || (regs[i].away && regs[i].location.IsImm())) {
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X64Reg xr = GetFreeXReg();
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if (xregs[xr].dirty) PanicAlert("Xreg already dirty");
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if (xregs[xr].allocLocked) PanicAlert("GetFreeXReg returned locked register");
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xregs[xr].free = false;
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xregs[xr].mipsReg = i;
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xregs[xr].dirty = makeDirty || regs[i].location.IsImm();
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OpArg newloc = ::Gen::R(xr);
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if (doLoad) {
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// Force ZERO to be 0.
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if (i == MIPS_REG_ZERO)
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emit->MOV(32, newloc, Imm32(0));
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else
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emit->MOV(32, newloc, regs[i].location);
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}
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for (int j = 0; j < 32; j++) {
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if (i != MIPSGPReg(j) && regs[j].location.IsSimpleReg(xr)) {
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ERROR_LOG(JIT, "BindToRegister: Strange condition");
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Crash();
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}
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}
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regs[i].away = true;
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regs[i].location = newloc;
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} else {
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// reg location must be simplereg; memory locations
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// and immediates are taken care of above.
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xregs[RX(i)].dirty |= makeDirty;
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}
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if (xregs[RX(i)].allocLocked) {
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PanicAlert("Seriously WTF, this reg should have been flushed");
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}
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}
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void GPRRegCache::StoreFromRegister(MIPSGPReg i) {
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if (regs[i].away) {
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bool doStore;
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if (regs[i].location.IsSimpleReg()) {
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X64Reg xr = RX(i);
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xregs[xr].free = true;
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xregs[xr].mipsReg = MIPS_REG_INVALID;
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doStore = xregs[xr].dirty;
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xregs[xr].dirty = false;
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} else {
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//must be immediate - do nothing
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doStore = true;
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}
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OpArg newLoc = GetDefaultLocation(i);
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// But never store to ZERO.
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if (doStore && i != MIPS_REG_ZERO)
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emit->MOV(32, newLoc, regs[i].location);
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regs[i].location = newLoc;
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regs[i].away = false;
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}
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}
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void GPRRegCache::Flush() {
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for (int i = 0; i < NUM_X_REGS; i++) {
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if (xregs[i].allocLocked)
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PanicAlert("Someone forgot to unlock X64 reg %i.", i);
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}
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for (int i = 0; i < NUM_MIPS_GPRS; i++) {
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const MIPSGPReg r = MIPSGPReg(i);
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if (regs[i].locked) {
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PanicAlert("Somebody forgot to unlock MIPS reg %i.", i);
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}
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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X64Reg xr = RX(r);
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StoreFromRegister(r);
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xregs[xr].dirty = false;
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}
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else if (regs[i].location.IsImm()) {
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StoreFromRegister(r);
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} else {
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_assert_msg_(JIT,0,"Jit64 - Flush unhandled case, reg %i PC: %08x", i, mips->pc);
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}
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}
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}
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}
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void GPRRegCache::GetState(GPRRegCacheState &state) const {
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memcpy(state.regs, regs, sizeof(regs));
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memcpy(state.xregs, xregs, sizeof(xregs));
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}
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void GPRRegCache::RestoreState(const GPRRegCacheState state) {
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memcpy(regs, state.regs, sizeof(regs));
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memcpy(xregs, state.xregs, sizeof(xregs));
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}
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