mirror of
https://github.com/hrydgard/ppsspp.git
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449 lines
14 KiB
C++
449 lines
14 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM64)
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#include "Core/MemMap.h"
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#include "Core/Config.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/ARM64/Arm64Jit.h"
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#include "Core/MIPS/ARM64/Arm64RegCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp {
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using namespace Arm64Gen;
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using namespace Arm64JitConstants;
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// Destroys SCRATCH2
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void Arm64Jit::SetScratch1ToEffectiveAddress(MIPSGPReg rs, s16 offset) {
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if (offset) {
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ADDI2R(SCRATCH1, gpr.R(rs), offset, SCRATCH2);
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} else {
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MOV(SCRATCH1, gpr.R(rs));
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}
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}
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std::vector<FixupBranch> Arm64Jit::SetScratch1ForSafeAddress(MIPSGPReg rs, s16 offset, ARM64Reg tempReg) {
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std::vector<FixupBranch> skips;
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SetScratch1ToEffectiveAddress(rs, offset);
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// We can do this a little smarter by shifting out the lower 8 bits, since blocks are 0x100 aligned.
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// PSP_GetUserMemoryEnd() is dynamic, but the others encode to imms just fine.
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// So we only need to safety check the one value.
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// This is because ARM64 immediates for many instructions like CMP can only encode
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// immediates up to 12 bits, shifted by 12 or not.
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if ((PSP_GetUserMemoryEnd() & 0x000FFFFF) == 0) {
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// In other words, shift right 8, and kill off the top 4 bits as we don't want them involved in the ocmpares.
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UBFX(tempReg, SCRATCH1, 8, 24 - 4);
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// Now check if we're higher than that.
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CMPI2R(tempReg, PSP_GetUserMemoryEnd() >> 8);
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} else {
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// Compare first using the tempReg (need it because we have a full 28-bit value), then shift into it.
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ANDI2R(SCRATCH1, SCRATCH1, 0x0FFFFFFF);
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CMPI2R(SCRATCH1, PSP_GetUserMemoryEnd(), tempReg);
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UBFX(tempReg, SCRATCH1, 8, 24);
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}
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skips.push_back(B(CC_HS));
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// If its higher than memory start and we didn't skip yet, it must be good. Hurray.
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CMPI2R(tempReg, PSP_GetKernelMemoryBase() >> 8);
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FixupBranch inRAM = B(CC_HS);
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// If we got here and it's higher, then it's between VRAM and RAM - skip.
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CMPI2R(tempReg, PSP_GetVidMemEnd() >> 8);
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skips.push_back(B(CC_HS));
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// And if it's higher the VRAM and we're still here again, it's in VRAM.
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CMPI2R(tempReg, PSP_GetVidMemBase() >> 8);
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FixupBranch inVRAM = B(CC_HS);
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// Last gap, this is between SRAM and VRAM. Skip it.
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CMPI2R(tempReg, PSP_GetScratchpadMemoryEnd() >> 8);
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skips.push_back(B(CC_HS));
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// And for lower than SRAM, we just skip again.
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CMPI2R(tempReg, PSP_GetScratchpadMemoryBase() >> 8);
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skips.push_back(B(CC_LO));
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// At this point, we're either in SRAM (above) or in RAM/VRAM.
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SetJumpTarget(inRAM);
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SetJumpTarget(inVRAM);
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return skips;
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}
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void Arm64Jit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op & 0xFFFF);
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (!js.inDelaySlot) {
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// Optimisation: Combine to single unaligned load/store
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bool isLeft = (o == 34 || o == 42);
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Find a matching shift in opposite direction with opposite offset.
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if (nextOp == (isLeft ? (op.encoding + (4 << 26) - 3) : (op.encoding - (4 << 26) + 3))) {
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EatInstruction(nextOp);
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nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw
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Comp_ITypeMem(nextOp);
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return;
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}
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}
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u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
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std::vector<FixupBranch> skips;
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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// Need to initialize since this only loads part of the register.
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// But rs no longer matters (even if rs == rt) since we have the address.
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gpr.MapReg(rt, load ? MAP_DIRTY : 0);
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gpr.SetRegImm(SCRATCH1, iaddr & ~3);
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u8 shift = (iaddr & 3) * 8;
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switch (o) {
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case 34: // lwl
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LDR(SCRATCH1, MEMBASEREG, SCRATCH1);
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ANDI2R(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift, INVALID_REG);
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ORR(gpr.R(rt), gpr.R(rt), SCRATCH1, ArithOption(gpr.R(rt), ST_LSL, 24 - shift));
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break;
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case 38: // lwr
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LDR(SCRATCH1, MEMBASEREG, SCRATCH1);
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ANDI2R(gpr.R(rt), gpr.R(rt), 0xffffff00 << (24 - shift), INVALID_REG);
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ORR(gpr.R(rt), gpr.R(rt), SCRATCH1, ArithOption(gpr.R(rt), ST_LSR, shift));
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break;
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case 42: // swl
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LDR(SCRATCH2, MEMBASEREG, SCRATCH1);
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ANDI2R(SCRATCH2, SCRATCH2, 0xffffff00 << shift, INVALID_REG);
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ORR(SCRATCH2, SCRATCH2, gpr.R(rt), ArithOption(gpr.R(rt), ST_LSR, 24 - shift));
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STR(SCRATCH2, MEMBASEREG, SCRATCH1);
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break;
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case 46: // swr
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LDR(SCRATCH2, MEMBASEREG, SCRATCH1);
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ANDI2R(SCRATCH2, SCRATCH2, 0x00ffffff >> (24 - shift), INVALID_REG);
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ORR(SCRATCH2, SCRATCH2, gpr.R(rt), ArithOption(gpr.R(rt), ST_LSL, shift));
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STR(SCRATCH2, MEMBASEREG, SCRATCH1);
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break;
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}
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return;
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}
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_dbg_assert_msg_(JIT, !gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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if (load) {
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gpr.MapDirtyIn(rt, rs, false);
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} else {
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gpr.MapInIn(rt, rs);
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}
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gpr.SpillLock(rt);
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gpr.SpillLock(rs);
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// Need to get temps before skipping safe mem.
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ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR();
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ARM64Reg LR_SCRATCH4 = o == 42 || o == 46 ? gpr.GetAndLockTempR() : INVALID_REG;
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if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
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skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
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} else {
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SetScratch1ToEffectiveAddress(rs, offset);
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}
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// Here's our shift amount.
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ANDI2R(SCRATCH2, SCRATCH1, 3);
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LSL(SCRATCH2, SCRATCH2, 3);
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// Now align the address for the actual read.
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ANDI2R(SCRATCH1, SCRATCH1, ~3U);
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switch (o) {
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case 34: // lwl
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MOVI2R(LR_SCRATCH3, 0x00ffffff);
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LDR(SCRATCH1, MEMBASEREG, ArithOption(SCRATCH1));
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LSRV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(gpr.R(rt), gpr.R(rt), LR_SCRATCH3);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSLV(SCRATCH1, SCRATCH1, SCRATCH2);
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ORR(gpr.R(rt), gpr.R(rt), SCRATCH1);
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break;
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case 38: // lwr
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MOVI2R(LR_SCRATCH3, 0xffffff00);
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LDR(SCRATCH1, MEMBASEREG, ArithOption(SCRATCH1));
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LSRV(SCRATCH1, SCRATCH1, SCRATCH2);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSLV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(gpr.R(rt), gpr.R(rt), LR_SCRATCH3);
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ORR(gpr.R(rt), gpr.R(rt), SCRATCH1);
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break;
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case 42: // swl
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MOVI2R(LR_SCRATCH3, 0xffffff00);
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LDR(LR_SCRATCH4, MEMBASEREG, ArithOption(SCRATCH1));
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LSLV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSRV(LR_SCRATCH3, gpr.R(rt), SCRATCH2);
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ORR(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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STR(LR_SCRATCH4, MEMBASEREG, ArithOption(SCRATCH1));
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break;
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case 46: // swr
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MOVI2R(LR_SCRATCH3, 0x00ffffff);
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LDR(LR_SCRATCH4, MEMBASEREG, ArithOption(SCRATCH1));
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSRV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSLV(LR_SCRATCH3, gpr.R(rt), SCRATCH2);
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ORR(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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STR(LR_SCRATCH4, MEMBASEREG, ArithOption(SCRATCH1));
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break;
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}
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for (auto skip : skips) {
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SetJumpTarget(skip);
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}
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gpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_ITypeMem(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op & 0xFFFF);
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bool load = false;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (((op >> 29) & 1) == 0 && rt == MIPS_REG_ZERO) {
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// Don't load anything into $zr
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return;
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}
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u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
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std::vector<FixupBranch> skips;
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ARM64Reg targetReg = INVALID_REG;
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ARM64Reg addrReg = INVALID_REG;
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int dataSize = 4;
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switch (o) {
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case 37:
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case 33:
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dataSize = 2;
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break;
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case 36:
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case 32:
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dataSize = 1;
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break;
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// Store
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case 41:
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dataSize = 2;
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break;
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case 40:
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dataSize = 1;
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break;
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}
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switch (o) {
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case 32: //lb
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case 33: //lh
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case 35: //lw
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case 36: //lbu
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case 37: //lhu
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load = true;
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case 40: //sb
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case 41: //sh
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case 43: //sw
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if (jo.cachePointers && g_Config.bFastMemory) {
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// ARM has smaller load/store immediate displacements than MIPS, 12 bits - and some memory ops only have 8 bits.
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int offsetRange = 0x3ff;
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if (o == 41 || o == 33 || o == 37 || o == 32)
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offsetRange = 0xff; // 8 bit offset only
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if (!gpr.IsImm(rs) && rs != rt && (offset <= offsetRange) && offset >= 0 &&
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(dataSize == 1 || (offset & (dataSize - 1)) == 0)) { // Check that the offset is aligned to the access size as that's required for INDEX_UNSIGNED encodings. we can get here through fallback from lwl/lwr
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gpr.SpillLock(rs, rt);
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gpr.MapRegAsPointer(rs);
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// For a store, try to avoid mapping a reg if not needed.
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targetReg = load ? INVALID_REG : gpr.TryMapTempImm(rt);
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if (targetReg == INVALID_REG) {
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gpr.MapReg(rt, load ? MAP_NOINIT : 0);
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targetReg = gpr.R(rt);
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}
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switch (o) {
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case 35: LDR(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 37: LDRH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 33: LDRSH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 36: LDRB(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 32: LDRSB(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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// Store
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case 43: STR(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 41: STRH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 40: STRB(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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}
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gpr.ReleaseSpillLocksAndDiscardTemps();
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break;
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}
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}
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if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) {
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// We're storing an immediate value, let's see if we can optimize rt.
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if (!gpr.IsImm(rs) || offset == 0) {
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// In this case, we're always going to need rs mapped, which may flush the temp imm.
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// We handle that in the cases below since targetReg is INVALID_REG.
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gpr.MapIn(rs);
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}
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targetReg = gpr.TryMapTempImm(rt);
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}
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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if (offset == 0) {
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// It was already safe. Let's shove it into a reg and use it directly.
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if (targetReg == INVALID_REG) {
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load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
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targetReg = gpr.R(rt);
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}
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addrReg = gpr.R(rs);
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} else {
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// In this case, only map rt. rs+offset will be in SCRATCH1.
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if (targetReg == INVALID_REG) {
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gpr.MapReg(rt, load ? MAP_NOINIT : 0);
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targetReg = gpr.R(rt);
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}
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gpr.SetRegImm(SCRATCH1, iaddr);
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addrReg = SCRATCH1;
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}
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} else {
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// This actually gets hit in micro machines! rs = ZR rt = ZR. Probably a bug.
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// Leaving this a debug assert for future investigation.
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_dbg_assert_msg_(JIT, !gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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// If we already have a targetReg, we optimized an imm, and rs is already mapped.
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if (targetReg == INVALID_REG) {
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load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
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targetReg = gpr.R(rt);
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}
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if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
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skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
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} else {
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SetScratch1ToEffectiveAddress(rs, offset);
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}
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addrReg = SCRATCH1;
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}
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switch (o) {
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// Load
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case 35: LDR(targetReg, MEMBASEREG, addrReg); break;
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case 37: LDRH(targetReg, MEMBASEREG, addrReg); break;
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case 33: LDRSH(targetReg, MEMBASEREG, addrReg); break;
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case 36: LDRB(targetReg, MEMBASEREG, addrReg); break;
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case 32: LDRSB(targetReg, MEMBASEREG, addrReg); break;
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// Store
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case 43: STR(targetReg, MEMBASEREG, addrReg); break;
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case 41: STRH(targetReg, MEMBASEREG, addrReg); break;
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case 40: STRB(targetReg, MEMBASEREG, addrReg); break;
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}
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for (auto skip : skips) {
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SetJumpTarget(skip);
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// TODO: Could clear to zero here on load, if skipping this for good reads.
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}
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break;
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case 34: //lwl
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case 38: //lwr
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load = true;
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case 42: //swl
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case 46: //swr
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Comp_ITypeMemLR(op, load);
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void Arm64Jit::Comp_Cache(MIPSOpcode op) {
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// int imm = (s16)(op & 0xFFFF);
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// int rs = _RS;
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// int addr = R(rs) + imm;
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int func = (op >> 16) & 0x1F;
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// It appears that a cache line is 0x40 (64) bytes, loops in games
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// issue the cache instruction at that interval.
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// These codes might be PSP-specific, they don't match regular MIPS cache codes very well
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switch (func) {
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// Icache
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case 8:
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// Invalidate the instruction cache at this address
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DISABLE;
|
|
break;
|
|
// Dcache
|
|
case 24:
|
|
// "Create Dirty Exclusive" - for avoiding a cacheline fill before writing to it.
|
|
// Will cause garbage on the real machine so we just ignore it, the app will overwrite the cacheline.
|
|
break;
|
|
case 25: // Hit Invalidate - zaps the line if present in cache. Should not writeback???? scary.
|
|
// No need to do anything.
|
|
break;
|
|
case 27: // D-cube. Hit Writeback Invalidate. Tony Hawk Underground 2
|
|
break;
|
|
case 30: // GTA LCS, a lot. Fill (prefetch). Tony Hawk Underground 2
|
|
break;
|
|
|
|
default:
|
|
DISABLE;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // PPSSPP_ARCH(ARM64)
|