mirror of
https://github.com/hrydgard/ppsspp.git
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525 lines
14 KiB
C++
525 lines
14 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// WARNING - THIS LIBRARY IS NOT THREAD SAFE!!!
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// http://www.csd.uwo.ca/~mburrel/stuff/ppc-asm.html
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// http://publib.boulder.ibm.com/infocenter/pseries/v5r3/index.jsp?topic=/com.ibm.aix.aixassem/doc/alangref/linkage_convent.htm
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// http://publib.boulder.ibm.com/infocenter/pseries/v5r3/index.jsp?topic=/com.ibm.aix.aixassem/doc/alangref/instruction_set.htm
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#ifndef _DOLPHIN_PPC_CODEGEN_
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#define _DOLPHIN_PPC_CODEGEN_
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#include "Common.h"
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#include "MemoryUtil.h"
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#include <vector>
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#undef _IP
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#undef R0
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#undef _SP
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#undef _LR
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#undef _PC
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#undef CALL
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namespace PpcGen
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{
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enum PPCReg
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{
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// GPRs (32)
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// Behaves as zero does in some instructions
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R0 = 0,
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// Stack pointer (SP)
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R1,
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// Reserved
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R2,
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// Used to pass integer function parameters and return values
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R3, R4,
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// Used to pass integer function parameters
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R5, R6, R7, R8, R9, R10,
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// General purpose
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R11,
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// Scratch
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R12,
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// Unused by the compiler reserved
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R13,
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// General purpose
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R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25,
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R26, R27, R28, R29, R30, R31,
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// CRs (7)
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CR0 = 0,
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// FPRs (32)
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// Scratch
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FPR0 = 0,
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// Used to pass double word function parameters and return values
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FPR1, FPR2, FPR3, FPR4,
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FPR5, FPR6, FPR7, FPR8,
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FPR9, FPR10, FPR11, FPR12,
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FPR13,
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// General purpose
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FPR14, FPR15, FPR16, FPR17,
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FPR18, FPR19, FPR20, FPR21,
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FPR22, FPR23, FPR24, FPR25,
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FPR26, FPR27, FPR28, FPR29,
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FPR30, FPR31,
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// Vmx (128)
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VR0 = 0, VR1, VR2, VR3, VR4,
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VR5, VR6, VR7, VR8, VR9,
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VR10, VR11, VR12, VR13, VR14,
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VR15, VR16, VR17, VR18, VR19,
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VR20, VR21, VR22, VR23, VR24,
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VR25, VR26, VR27, VR28, VR29,
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VR30, VR31, VR32, VR33, VR34,
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VR35, VR36, VR37, VR38, VR39,
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VR40, VR41, VR42, VR43, VR44,
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VR45, VR46, VR47, VR48, VR49,
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VR50, VR51, VR52, VR53, VR54,
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VR55, VR56, VR57, VR58, VR59,
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VR60, VR61, VR62, VR63, VR64,
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VR65, VR66, VR67, VR68, VR69,
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VR70, VR71, VR72, VR73, VR74,
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VR75, VR76, VR77, VR78, VR79,
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VR80, VR81, VR82, VR83, VR84,
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VR85, VR86, VR87, VR88, VR89,
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VR90, VR91, VR92, VR93, VR94,
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VR95, VR96, VR97, VR98, VR99, //...
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// Others regs
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LR, CTR, XER, FPSCR,
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// End
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INVALID_REG = 0xFFFFFFFF
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};
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enum IntegerSize
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{
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I_I8 = 0,
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I_I16,
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I_I32,
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I_I64
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};
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enum
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{
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NUMGPRs = 31,
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};
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typedef const u8* JumpTarget;
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enum FixupBranchType {
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_B,
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_BEQ,
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_BNE,
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_BLT,
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_BLE,
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_BGT,
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_BGE,
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// Link register
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_BL
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};
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struct FixupBranch
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{
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u8 *ptr;
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u32 condition; // Remembers our codition at the time
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FixupBranchType type; //0 = B 1 = BL
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};
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class PPCXEmitter
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{
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private:
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u8 *code, *startcode;
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u8 *lastCacheFlushEnd;
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u32 condition;
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protected:
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// Write opcode
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inline void Write32(u32 value) {*(u32*)code = value; code+=4;}
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public:
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PPCXEmitter() : code(0), startcode(0), lastCacheFlushEnd(0) {
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}
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PPCXEmitter(u8 *code_ptr) {
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code = code_ptr;
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lastCacheFlushEnd = code_ptr;
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startcode = code_ptr;
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}
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virtual ~PPCXEmitter() {}
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void SetCodePtr(u8 *ptr);
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void ReserveCodeSpace(u32 bytes);
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr() const;
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void FlushIcache();
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void FlushIcacheSection(u8 *start, u8 *end);
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u8 *GetWritableCodePtr();
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// Special purpose instructions
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// Debug Breakpoint
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void BKPT(u16 arg);
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// Hint instruction
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void YIELD();
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// Do nothing
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void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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// FixupBranch ops
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FixupBranch B();
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FixupBranch BL();
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FixupBranch BNE();
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FixupBranch BLT();
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FixupBranch BLE();
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FixupBranch B_Cond(FixupBranchType type);
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void SetJumpTarget(FixupBranch const &branch);
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// Branch ops
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void B (const void *fnptr);
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void BL(const void *fnptr);
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void BA (const void *fnptr);
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void BLA(const void *fnptr);
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void BEQ(const void *fnptr);
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void BNE(const void *fnptr);
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void BLE(const void *fnptr);
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void BLT(const void *fnptr);
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void BGT(const void *fnptr);
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void BEQ (PPCReg r);
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void BLR();
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void BGTLR(); // ??? used ?
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void BLTCTR();
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void BGTCTR();
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void BLECTR();
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void BGECTR();
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void BCTRL ();
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void BCTR();
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// Link Register
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void MFLR(PPCReg r);
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void MTLR(PPCReg r);
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void MTCTR(PPCReg r);
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// Logical Ops
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void AND (PPCReg Rs, PPCReg Ra, PPCReg Rb);
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void ANDI (PPCReg Rdest, PPCReg Ra, unsigned short imm);
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void ANDIS(PPCReg Rdest, PPCReg Ra, unsigned short imm);
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void NAND (PPCReg Rs, PPCReg Ra, PPCReg Rb);
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void OR (PPCReg Rs, PPCReg Ra, PPCReg Rb);
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void ORI (PPCReg Rdest, PPCReg Ra, unsigned short imm);
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void NOR (PPCReg Rs, PPCReg Ra, PPCReg Rb);
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void XOR (PPCReg Rs, PPCReg Ra, PPCReg Rb);
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void XORI (PPCReg Rdest, PPCReg Ra, unsigned short imm);
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void NEG (PPCReg Rs, PPCReg Ra);
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void EQV (PPCReg a, PPCReg b, PPCReg c);
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// Arithmetics ops
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void ADD (PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void ADDI (PPCReg Rd, PPCReg Ra, short imm);
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void ADDIS (PPCReg Rd, PPCReg Ra, short imm);
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void ADDC (PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void ADDZE (PPCReg Rd, PPCReg Ra);
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void SUB (PPCReg Rd, PPCReg Ra, PPCReg Rb) {
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// reverse ?
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SUBF(Rd, Rb, Ra);
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}
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// if RCFlags update CR0
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void SUBF (PPCReg Rd, PPCReg Ra, PPCReg Rb, int RCFlags = 0);
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void SUBFIC (PPCReg Rt, PPCReg Ra, short imm);
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void SUBFC (PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void SUBFE (PPCReg Rd, PPCReg Ra, PPCReg Rb);
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// integer multiplication ops
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void DIVW (PPCReg Rt, PPCReg Ra, PPCReg Rb);
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void DIVWU (PPCReg Rt, PPCReg Ra, PPCReg Rb);
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void MULLW (PPCReg Rt, PPCReg Ra, PPCReg Rb);
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void MULHW (PPCReg Rt, PPCReg Ra, PPCReg Rb);
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void MULHWU (PPCReg Rt, PPCReg Ra, PPCReg Rb);
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// Memory load/store operations
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void LI (PPCReg dest, unsigned short imm);
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void LIS (PPCReg dest, unsigned short imm);
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// dest = LIS(imm) + ORI(+imm)
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void MOVI2R (PPCReg dest, unsigned int imm);
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// 8bit
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void LBZ (PPCReg dest, PPCReg src, int offset = 0);
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void LBZX (PPCReg dest, PPCReg a, PPCReg b);
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// 16bit
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void LHZ (PPCReg dest, PPCReg src, int offset = 0);
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void LHBRX (PPCReg dest, PPCReg src, PPCReg offset);
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// 32 bit
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void LWZ (PPCReg dest, PPCReg src, int offset = 0);
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void LWBRX (PPCReg dest, PPCReg src, PPCReg offset);
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// 64 bit
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void LD (PPCReg dest, PPCReg src, int offset = 0);
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// 8 bit
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void STB (PPCReg dest, PPCReg src, int offset = 0);
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void STBX (PPCReg dest, PPCReg a, PPCReg b);
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// 16 bit
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void STH (PPCReg dest, PPCReg src, int offset = 0);
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void STHBRX (PPCReg dest, PPCReg src, PPCReg offset);
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// 32 bit
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void STW (PPCReg dest, PPCReg src, int offset = 0);
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void STWU (PPCReg dest, PPCReg src, int offset = 0);
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void STWBRX (PPCReg dest, PPCReg src, PPCReg offset);
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// 64 bit
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void STD (PPCReg dest, PPCReg src, int offset = 0);
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// sign
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void EXTSB (PPCReg dest, PPCReg src);
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void EXTSH (PPCReg dest, PPCReg src);
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void EXTSW (PPCReg dest, PPCReg src);
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//
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void RLWINM (PPCReg dest, PPCReg src, int shift, int start, int end);
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void RLDICL (PPCReg Rt, PPCReg Rs, int sh, int mb);
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// Shift Instructions
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void SRAW (PPCReg dest, PPCReg src, PPCReg shift);
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void SRAWI (PPCReg dest, PPCReg src, unsigned short imm);
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void SLW (PPCReg dest, PPCReg src, PPCReg shift);
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void SLWI (PPCReg dest, PPCReg src, unsigned short imm);
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void SRW (PPCReg dest, PPCReg src, PPCReg shift);
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void SRWI (PPCReg dest, PPCReg src, unsigned short imm);
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void ROTRW (PPCReg dest, PPCReg src, PPCReg shift);
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void ROTRWI (PPCReg dest, PPCReg src, unsigned short imm);
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void ROTLW (PPCReg dest, PPCReg src, PPCReg shift);
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void ROTLWI (PPCReg dest, PPCReg src, unsigned short imm);
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// Compare
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enum CONDITION_REGISTER{
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CR0,
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CR1,
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CR2,
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CR3,
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CR4,
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CR5,
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CR6,
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CR7
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};
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void CROR (int bt, int ba, int bb);
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void CMPLI (PPCReg dest, unsigned short imm);
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void CMPI (PPCReg dest, unsigned short imm);
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void CMPL (PPCReg a, PPCReg b, CONDITION_REGISTER cr = CR0);
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void CMP (PPCReg a, PPCReg b, CONDITION_REGISTER cr = CR0);
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void MFCR (PPCReg dest);
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void MTCR (PPCReg dest);
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void ISEL (PPCReg Rt, PPCReg Ra, PPCReg Rb, CONDITION_REGISTER cr = CR0);
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void Prologue();
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void Epilogue();
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// Debug !
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void Break() {
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Write32(0x0FE00016);
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}
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void MR (PPCReg to, PPCReg from) {
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OR(to, from, from);
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}
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// Fpu
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void LFS (PPCReg FRt, PPCReg Ra, unsigned short offset = 0);
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void LFD (PPCReg FRt, PPCReg Ra, unsigned short offset = 0);
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void SFS (PPCReg FRt, PPCReg Ra, unsigned short offset = 0);
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void SFD (PPCReg FRt, PPCReg Ra, unsigned short offset = 0);
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void SaveFloatSwap(PPCReg FRt, PPCReg Ra, PPCReg offset);
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void LoadFloatSwap(PPCReg FRt, PPCReg Ra, PPCReg offset);
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// dest = LIS(imm) + ORI(+imm)
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void MOVI2F (PPCReg dest, float imm, bool negate = false);
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// Fpu move instruction
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void FMR (PPCReg FRt, PPCReg FRb);
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// fpu
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void MTFSB0 (int bt);
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void FCFID (PPCReg FRt, PPCReg FRb);
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void FCTID (PPCReg FRt, PPCReg FRb);
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void FRSP (PPCReg FRt, PPCReg FRb);
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void FCTIW (PPCReg FRt, PPCReg FRb);
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void STFIWX (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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// Fpu
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void FNEG (PPCReg FRt, PPCReg FRb);
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void FABS (PPCReg FRt, PPCReg FRb);
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void FNABS (PPCReg FRt, PPCReg FRb);
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void FCPSGN (PPCReg FRt, PPCReg FRb);
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// Fpu arith
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void FADD (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FSUB (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FADDS (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FSUBS (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FMUL (PPCReg FRt, PPCReg FRa, PPCReg FRc);
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void FMULS (PPCReg FRt, PPCReg FRa, PPCReg FRc);
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void FDIV (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FDIVS (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FSQRT (PPCReg FRt, PPCReg FRb);
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void FSQRTS (PPCReg FRt, PPCReg FRb);
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void FSQRTE (PPCReg FRt, PPCReg FRb);
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void FSQRTES(PPCReg FRt, PPCReg FRb);
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void FRE (PPCReg FRt, PPCReg FRb);
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void FRES (PPCReg FRt, PPCReg FRb);
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// FSEL ...
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void FSEL (PPCReg FRt, PPCReg FRa, PPCReg FRc, PPCReg FRb);
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void FMIN (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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void FMAX (PPCReg FRt, PPCReg FRa, PPCReg FRb);
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// Fpu mul add
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void FMADD (PPCReg FRt, PPCReg FRa, PPCReg FRc, PPCReg FRb);
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void FMSUB (PPCReg FRt, PPCReg FRa, PPCReg FRc, PPCReg FRb);
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void FMADDS (PPCReg FRt, PPCReg FRa, PPCReg FRc, PPCReg FRb);
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void FMSUBS (PPCReg FRt, PPCReg FRa, PPCReg FRc, PPCReg FRb);
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// Fpu compare
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void FCMPU (int Bf, PPCReg FRa, PPCReg FRb); // unordered
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void FCMPO (int Bf, PPCReg FRa, PPCReg FRb); // ordered
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// Fpu convert
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void FRIN (PPCReg FRt, PPCReg FRb); // round
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void FRIZ (PPCReg FRt, PPCReg FRb); // trunc
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void FRIP (PPCReg FRt, PPCReg FRb); // ceil
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void FRIM (PPCReg FRt, PPCReg FRb); // floor
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// VPU - lvx128
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void LoadVector(PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void SaveVector(PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void LoadVectorSwap(PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void SaveVectorSwap(PPCReg Rd, PPCReg Ra, PPCReg Rb);
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void MOVI2V (PPCReg dest, float imm);
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void VADDFP (PPCReg Rd, PPCReg Ra); // Vector Add Floating Point
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void VMADDFP (PPCReg Rd, PPCReg Ra, PPCReg Rb); // Vector Multiply Add Floating Point
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void VMAXFP (PPCReg Rd, PPCReg Ra); // Vector Maximum Floating Point
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void VMINFP (PPCReg Rd, PPCReg Ra); // Vector Minimum Floating Point
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void VMSUM3FP (PPCReg Rd, PPCReg Ra); // 3-operand Dot Product
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void VMSUM4FP (PPCReg Rd, PPCReg Ra); // 4-operand Dot Product
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void VMULFP (PPCReg Rd, PPCReg Ra); // Vector Multiply Floating Point
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void VNMSUBFP (PPCReg Rd, PPCReg Ra, PPCReg Rb); // Vector Negate Multiply-Subtract Floating Point
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void VSUBFP (PPCReg Rd, PPCReg Ra); // Vector Subtract Floating Point
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void VCMPBFP (PPCReg Rd, PPCReg Ra); // Vector Compare Bounds Floating Point
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void VCMPEQFP (PPCReg Rd, PPCReg Ra); // Vector Compare Equal-to-Floating Point
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void VCMPGEFP (PPCReg Rd, PPCReg Ra); // Vector Compare Greater-Than-or-Equal-to Floating Point
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void VCMPGTFP (PPCReg Rd, PPCReg Ra); // Vector Compare Greater-Than Floating Point
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void QuickCallFunction(void *func);
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protected:
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}; // class PPCXEmitter
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// You get memory management for free, plus, you can use all the MOV etc functions without
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// having to prefix them with gen-> or something similar.
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class PPCXCodeBlock : public PPCXEmitter
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{
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protected:
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u8 *region;
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size_t region_size;
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public:
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PPCXCodeBlock() : region(NULL), region_size(0) {}
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virtual ~PPCXCodeBlock() { if (region) FreeCodeSpace(); }
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// Call this before you generate any code.
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void AllocCodeSpace(int size)
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{
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region_size = size;
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region = (u8*)AllocateExecutableMemory(region_size);
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SetCodePtr(region);
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}
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// Always clear code space with breakpoints, so that if someone accidentally executes
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// uninitialized, it just breaks into the debugger.
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void ClearCodeSpace()
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{
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// x86/64: 0xCC = breakpoint
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memset(region, 0xCC, region_size);
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ResetCodePtr();
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}
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// Call this when shutting down. Don't rely on the destructor, even though it'll do the job.
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void FreeCodeSpace()
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{
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region = NULL;
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region_size = 0;
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}
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bool IsInSpace(const u8 *ptr) const
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|
{
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return ptr >= region && ptr < region + region_size;
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}
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// Cannot currently be undone. Will write protect the entire code region.
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// Start over if you need to change the code (call FreeCodeSpace(), AllocCodeSpace()).
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void WriteProtect()
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|
{
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//WriteProtectMemory(region, region_size, true);
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|
}
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void UnWriteProtect()
|
|
{
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//UnWriteProtectMemory(region, region_size, false);
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}
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|
|
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void ResetCodePtr()
|
|
{
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SetCodePtr(region);
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}
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|
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size_t GetSpaceLeft() const
|
|
{
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return region_size - (GetCodePtr() - region);
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}
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|
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u8 *GetBasePtr() {
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|
return region;
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|
}
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|
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size_t GetOffset(const u8 *ptr) const {
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|
return ptr - region;
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|
}
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|
};
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} // namespace
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#endif // _DOLPHIN_INTEL_CODEGEN_
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