mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-11-23 13:30:02 +00:00
321 lines
10 KiB
C++
321 lines
10 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include "Common/Log.h"
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#include "Core/CoreTiming.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/x86/X64IRJit.h"
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#include "Core/MIPS/x86/X64IRRegCache.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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#include "Core/System.h"
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namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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static const bool enableDebug = false;
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static const bool enableDisasm = false;
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static void ShowPC(void *membase, void *jitbase) {
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static int count = 0;
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if (currentMIPS) {
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u32 downcount = currentMIPS->downcount;
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ERROR_LOG(JIT, "[%08x] ShowPC Downcount : %08x %d %p %p", currentMIPS->pc, downcount, count, membase, jitbase);
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} else {
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ERROR_LOG(JIT, "Universe corrupt?");
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}
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//if (count > 2000)
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// exit(0);
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count++;
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}
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void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) {
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// This will be used as a writable scratch area, always 32-bit accessible.
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const u8 *start = AlignCodePage();
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if (DebugProfilerEnabled()) {
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ProtectMemoryPages(start, GetMemoryProtectPageSize(), MEM_PROT_READ | MEM_PROT_WRITE);
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hooks_.profilerPC = (uint32_t *)GetWritableCodePtr();
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Write32(0);
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hooks_.profilerStatus = (IRProfilerStatus *)GetWritableCodePtr();
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Write32(0);
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}
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EmitFPUConstants();
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EmitVecConstants();
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const u8 *disasmStart = AlignCodePage();
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BeginWrite(GetMemoryProtectPageSize());
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jo.downcountInRegister = false;
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#if PPSSPP_ARCH(AMD64)
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bool jitbaseInR15 = false;
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int jitbaseCtxDisp = 0;
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// We pre-bake the MIPS_EMUHACK_OPCODE subtraction into our jitbase value.
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intptr_t jitbase = (intptr_t)GetBasePtr() - MIPS_EMUHACK_OPCODE;
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if ((jitbase < -0x80000000LL || jitbase > 0x7FFFFFFFLL) && !Accessible((const u8 *)&mipsState->f[0], (const u8 *)jitbase)) {
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jo.reserveR15ForAsm = true;
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jitbaseInR15 = true;
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} else {
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jo.downcountInRegister = true;
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jo.reserveR15ForAsm = true;
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if (jitbase < -0x80000000LL || jitbase > 0x7FFFFFFFLL) {
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jitbaseCtxDisp = (int)(jitbase - (intptr_t)&mipsState->f[0]);
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}
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}
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#endif
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if (jo.useStaticAlloc && false) {
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saveStaticRegisters_ = AlignCode16();
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if (jo.downcountInRegister)
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MOV(32, MDisp(CTXREG, downcountOffset), R(DOWNCOUNTREG));
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//regs_.EmitSaveStaticRegisters();
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RET();
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// Note: needs to not modify EAX, or to save it if it does.
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loadStaticRegisters_ = AlignCode16();
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//regs_.EmitLoadStaticRegisters();
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if (jo.downcountInRegister)
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MOV(32, R(DOWNCOUNTREG), MDisp(CTXREG, downcountOffset));
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RET();
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} else {
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saveStaticRegisters_ = nullptr;
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loadStaticRegisters_ = nullptr;
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}
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restoreRoundingMode_ = AlignCode16();
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{
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STMXCSR(MDisp(CTXREG, tempOffset));
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// Clear the rounding mode and flush-to-zero bits back to 0.
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AND(32, MDisp(CTXREG, tempOffset), Imm32(~(7 << 13)));
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LDMXCSR(MDisp(CTXREG, tempOffset));
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RET();
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}
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applyRoundingMode_ = AlignCode16();
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{
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MOV(32, R(SCRATCH1), MDisp(CTXREG, fcr31Offset));
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AND(32, R(SCRATCH1), Imm32(0x01000003));
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// If it's 0 (nearest + no flush0), we don't actually bother setting - we cleared the rounding
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// mode out in restoreRoundingMode anyway. This is the most common.
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FixupBranch skip = J_CC(CC_Z);
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STMXCSR(MDisp(CTXREG, tempOffset));
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// The MIPS bits don't correspond exactly, so we have to adjust.
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// 0 -> 0 (skip2), 1 -> 3, 2 -> 2 (skip2), 3 -> 1
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TEST(8, R(AL), Imm8(1));
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FixupBranch skip2 = J_CC(CC_Z);
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XOR(32, R(SCRATCH1), Imm8(2));
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SetJumpTarget(skip2);
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// Adjustment complete, now reconstruct MXCSR
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SHL(32, R(SCRATCH1), Imm8(13));
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// Before setting new bits, we must clear the old ones.
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// Clearing bits 13-14 (rounding mode) and 15 (flush to zero.)
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AND(32, MDisp(CTXREG, tempOffset), Imm32(~(7 << 13)));
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OR(32, MDisp(CTXREG, tempOffset), R(SCRATCH1));
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TEST(32, MDisp(CTXREG, fcr31Offset), Imm32(1 << 24));
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FixupBranch skip3 = J_CC(CC_Z);
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OR(32, MDisp(CTXREG, tempOffset), Imm32(1 << 15));
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SetJumpTarget(skip3);
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LDMXCSR(MDisp(CTXREG, tempOffset));
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SetJumpTarget(skip);
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RET();
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}
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hooks_.enterDispatcher = (IRNativeFuncNoArg)AlignCode16();
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ABI_PushAllCalleeSavedRegsAndAdjustStack();
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#if PPSSPP_ARCH(AMD64)
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// Two x64-specific statically allocated registers.
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MOV(64, R(MEMBASEREG), ImmPtr(Memory::base));
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if (jitbaseInR15)
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MOV(64, R(JITBASEREG), ImmPtr((const void *)jitbase));
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#endif
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// From the start of the FP reg, a single byte offset can reach all GPR + all FPR (but not VFPR.)
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MOV(PTRBITS, R(CTXREG), ImmPtr(&mipsState->f[0]));
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LoadStaticRegisters();
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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MovFromPC(SCRATCH1);
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WriteDebugPC(SCRATCH1);
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outerLoopPCInSCRATCH1_ = GetCodePtr();
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MovToPC(SCRATCH1);
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outerLoop_ = GetCodePtr();
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// Advance can change the downcount (or thread), so must save/restore around it.
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SaveStaticRegisters();
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RestoreRoundingMode(true);
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WriteDebugProfilerStatus(IRProfilerStatus::TIMER_ADVANCE);
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ABI_CallFunction(reinterpret_cast<void *>(&CoreTiming::Advance));
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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ApplyRoundingMode(true);
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LoadStaticRegisters();
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dispatcherCheckCoreState_ = GetCodePtr();
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// TODO: See if we can get the slice decrement to line up with IR.
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if (RipAccessible((const void *)&coreState)) {
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CMP(32, M(&coreState), Imm8(0)); // rip accessible
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} else {
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MOV(PTRBITS, R(RAX), ImmPtr((const void *)&coreState));
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CMP(32, MatR(RAX), Imm8(0));
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}
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FixupBranch badCoreState = J_CC(CC_NZ, true);
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if (jo.downcountInRegister) {
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TEST(32, R(DOWNCOUNTREG), R(DOWNCOUNTREG));
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} else {
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CMP(32, MDisp(CTXREG, downcountOffset), Imm8(0));
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}
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J_CC(CC_S, outerLoop_);
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FixupBranch skipToRealDispatch = J();
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dispatcherPCInSCRATCH1_ = GetCodePtr();
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MovToPC(SCRATCH1);
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hooks_.dispatcher = GetCodePtr();
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// TODO: See if we can get the slice decrement to line up with IR.
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if (jo.downcountInRegister) {
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TEST(32, R(DOWNCOUNTREG), R(DOWNCOUNTREG));
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} else {
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CMP(32, MDisp(CTXREG, downcountOffset), Imm8(0));
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}
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FixupBranch bail = J_CC(CC_S, true);
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SetJumpTarget(skipToRealDispatch);
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dispatcherNoCheck_ = GetCodePtr();
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// Debug
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if (enableDebug) {
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#if PPSSPP_ARCH(AMD64)
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if (jitbaseInR15) {
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ABI_CallFunctionAA(reinterpret_cast<void *>(&ShowPC), R(MEMBASEREG), R(JITBASEREG));
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} else if (jitbaseCtxDisp != 0) {
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LEA(64, SCRATCH1, MDisp(CTXREG, jitbaseCtxDisp));
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ABI_CallFunctionAA(reinterpret_cast<void *>(&ShowPC), R(MEMBASEREG), R(SCRATCH1));
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} else {
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ABI_CallFunctionAC(reinterpret_cast<void *>(&ShowPC), R(MEMBASEREG), (u32)jitbase);
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}
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#else
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ABI_CallFunctionCC(reinterpret_cast<void *>(&ShowPC), (u32)Memory::base, (u32)GetBasePtr());
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#endif
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}
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MovFromPC(SCRATCH1);
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WriteDebugPC(SCRATCH1);
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#ifdef MASKED_PSP_MEMORY
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AND(32, R(SCRATCH1), Imm32(Memory::MEMVIEW32_MASK));
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#endif
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hooks_.dispatchFetch = GetCodePtr();
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#if PPSSPP_ARCH(X86)
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_assert_msg_( Memory::base != 0, "Memory base bogus");
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MOV(32, R(SCRATCH1), MDisp(SCRATCH1, (u32)Memory::base));
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#elif PPSSPP_ARCH(AMD64)
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MOV(32, R(SCRATCH1), MComplex(MEMBASEREG, SCRATCH1, SCALE_1, 0));
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#endif
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_assert_msg_(MIPS_JITBLOCK_MASK == 0xFF000000, "Hardcoded assumption of emuhack mask");
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if (cpu_info.bBMI2) {
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RORX(32, EDX, R(SCRATCH1), 24);
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CMP(8, R(EDX), Imm8(MIPS_EMUHACK_OPCODE >> 24));
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} else {
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MOV(32, R(EDX), R(SCRATCH1));
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SHR(32, R(EDX), Imm8(24));
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CMP(32, R(EDX), Imm8(MIPS_EMUHACK_OPCODE >> 24));
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}
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FixupBranch needsCompile = J_CC(CC_NE);
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// We don't mask here - that's baked into jitbase.
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#if PPSSPP_ARCH(X86)
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LEA(32, SCRATCH1, MDisp(SCRATCH1, (u32)GetBasePtr() - MIPS_EMUHACK_OPCODE));
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#elif PPSSPP_ARCH(AMD64)
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if (jitbaseInR15) {
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ADD(64, R(SCRATCH1), R(JITBASEREG));
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} else if (jitbaseCtxDisp) {
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LEA(64, SCRATCH1, MComplex(CTXREG, SCRATCH1, SCALE_1, jitbaseCtxDisp));
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} else {
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// See above, reserveR15ForAsm is used when above 0x7FFFFFFF.
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LEA(64, SCRATCH1, MDisp(SCRATCH1, (s32)jitbase));
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}
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#endif
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JMPptr(R(SCRATCH1));
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SetJumpTarget(needsCompile);
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// No block found, let's jit. We don't need to save static regs, they're all callee saved.
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RestoreRoundingMode(true);
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WriteDebugProfilerStatus(IRProfilerStatus::COMPILING);
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ABI_CallFunction(&MIPSComp::JitAt);
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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ApplyRoundingMode(true);
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// Let's just dispatch again, we'll enter the block since we know it's there.
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JMP(dispatcherNoCheck_, true);
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SetJumpTarget(bail);
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if (RipAccessible((const void *)&coreState)) {
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CMP(32, M(&coreState), Imm8(0)); // rip accessible
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} else {
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MOV(PTRBITS, R(RAX), ImmPtr((const void *)&coreState));
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CMP(32, MatR(RAX), Imm8(0));
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}
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J_CC(CC_Z, outerLoop_, true);
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const uint8_t *quitLoop = GetCodePtr();
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SetJumpTarget(badCoreState);
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WriteDebugProfilerStatus(IRProfilerStatus::NOT_RUNNING);
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SaveStaticRegisters();
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RestoreRoundingMode(true);
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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hooks_.crashHandler = GetCodePtr();
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if (RipAccessible((const void *)&coreState)) {
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MOV(32, M(&coreState), Imm32(CORE_RUNTIME_ERROR));
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} else {
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MOV(PTRBITS, R(RAX), ImmPtr((const void *)&coreState));
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MOV(32, MatR(RAX), Imm32(CORE_RUNTIME_ERROR));
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}
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JMP(quitLoop, true);
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// Leave this at the end, add more stuff above.
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if (enableDisasm) {
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#if PPSSPP_ARCH(AMD64)
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std::vector<std::string> lines = DisassembleX86(disasmStart, (int)(GetCodePtr() - disasmStart));
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for (auto s : lines) {
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INFO_LOG(JIT, "%s", s.c_str());
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}
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#endif
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}
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// Let's spare the pre-generated code from unprotect-reprotect.
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AlignCodePage();
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jitStartOffset_ = (int)(GetCodePtr() - start);
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EndWrite();
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}
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} // namespace MIPSComp
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#endif
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