mirror of
https://github.com/hrydgard/ppsspp.git
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152 lines
5.2 KiB
C++
152 lines
5.2 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include "Common/x64Emitter.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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namespace X64IRJitConstants {
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#if PPSSPP_ARCH(AMD64)
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const Gen::X64Reg MEMBASEREG = Gen::RBX;
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const Gen::X64Reg CTXREG = Gen::R14;
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// Note: this is actually offset from the base.
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const Gen::X64Reg JITBASEREG = Gen::R15;
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const Gen::X64Reg DOWNCOUNTREG = Gen::R15;
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#else
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const Gen::X64Reg CTXREG = Gen::EBP;
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const Gen::X64Reg DOWNCOUNTREG = Gen::INVALID_REG;
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#endif
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const Gen::X64Reg SCRATCH1 = Gen::EAX;
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static constexpr auto downcountOffset = offsetof(MIPSState, downcount) - 128;
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static constexpr auto tempOffset = offsetof(MIPSState, temp) - 128;
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static constexpr auto fcr31Offset = offsetof(MIPSState, fcr31) - 128;
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static constexpr auto pcOffset = offsetof(MIPSState, pc) - 128;
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static constexpr auto mxcsrTempOffset = offsetof(MIPSState, mxcsrTemp) - 128;
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enum class X64Map : uint8_t {
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NONE = 0,
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// On 32-bit: EAX, EBX, ECX, EDX
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LOW_SUBREG = 0x10,
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// EDX/RDX for DIV/MUL/similar.
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HIGH_DATA = 0x20,
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// ECX/RCX only, for shifts.
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SHIFT = 0x30,
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// XMM0 for BLENDVPS, funcs.
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XMM0 = 0x40,
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MASK = 0xF0,
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};
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static inline MIPSMap operator |(const MIPSMap &lhs, const X64Map &rhs) {
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return MIPSMap((uint8_t)lhs | (uint8_t)rhs);
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}
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static inline X64Map operator |(const X64Map &lhs, const X64Map &rhs) {
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return X64Map((uint8_t)lhs | (uint8_t)rhs);
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}
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static inline X64Map operator &(const MIPSMap &lhs, const X64Map &rhs) {
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return X64Map((uint8_t)lhs & (uint8_t)rhs);
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}
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static inline X64Map operator &(const X64Map &lhs, const X64Map &rhs) {
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return X64Map((uint8_t)lhs & (uint8_t)rhs);
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}
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} // namespace X64IRJitConstants
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class X64IRRegCache : public IRNativeRegCacheBase {
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public:
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X64IRRegCache(MIPSComp::JitOptions *jo);
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void Init(Gen::XEmitter *emitter);
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// May fail and return INVALID_REG if it needs flushing.
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Gen::X64Reg TryMapTempImm(IRReg reg, X64IRJitConstants::X64Map flags = X64IRJitConstants::X64Map::NONE);
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// Returns an X64 register containing the requested MIPS register.
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Gen::X64Reg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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Gen::X64Reg MapGPR2(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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Gen::X64Reg MapGPRAsPointer(IRReg reg);
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Gen::X64Reg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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Gen::X64Reg MapVec4(IRReg first, MIPSMap mapFlags = MIPSMap::INIT);
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Gen::X64Reg MapWithFPRTemp(const IRInst &inst);
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void MapWithFlags(IRInst inst, X64IRJitConstants::X64Map destFlags, X64IRJitConstants::X64Map src1Flags = X64IRJitConstants::X64Map::NONE, X64IRJitConstants::X64Map src2Flags = X64IRJitConstants::X64Map::NONE);
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// Note: may change the high lanes of single-register XMMs.
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void FlushAll(bool gprs = true, bool fprs = true) override;
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void FlushBeforeCall();
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Gen::X64Reg GetAndLockTempGPR();
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Gen::X64Reg GetAndLockTempFPR();
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void ReserveAndLockXGPR(Gen::X64Reg r);
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Gen::OpArg R(IRReg preg);
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Gen::OpArg RPtr(IRReg preg);
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Gen::OpArg F(IRReg preg);
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Gen::X64Reg RX(IRReg preg); // Returns a cached register, while checking that it's NOT mapped as a pointer
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Gen::X64Reg RXPtr(IRReg preg); // Returns a cached register, if it has been mapped as a pointer
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Gen::X64Reg FX(IRReg preg);
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static bool HasLowSubregister(Gen::X64Reg reg);
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protected:
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const int *GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const override;
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void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override;
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void LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override;
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void StoreRegValue(IRReg mreg, uint32_t imm) override;
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bool TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) override;
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private:
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bool TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes);
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bool Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes);
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IRNativeReg GPRToNativeReg(Gen::X64Reg r) {
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return (IRNativeReg)r;
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}
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IRNativeReg XMMToNativeReg(Gen::X64Reg r) {
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return (IRNativeReg)(r + NUM_X_REGS);
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}
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Gen::X64Reg FromNativeReg(IRNativeReg r) {
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if (r >= NUM_X_REGS)
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return (Gen::X64Reg)(Gen::XMM0 + (r - NUM_X_REGS));
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return (Gen::X64Reg)(Gen::RAX + r);
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}
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Gen::XEmitter *emit_ = nullptr;
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enum {
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#if PPSSPP_ARCH(AMD64)
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NUM_X_REGS = 16,
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NUM_X_FREGS = 16,
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#elif PPSSPP_ARCH(X86)
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NUM_X_REGS = 8,
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NUM_X_FREGS = 8,
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#endif
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};
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};
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#endif
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