mirror of
https://github.com/hrydgard/ppsspp.git
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6108e36ae9
Add missing #include to various files. strings.h isn't provided by MSVC so we don't include it there; it's needed for other OSes/compilers. Get rid of pre-ISO-C malloc.h includes; malloc is provided by stdlib.h. Fixes some linuxisms. Prepend __builtin_ to __clear_cache, calling it without the prefix is a GNU extension.
448 lines
14 KiB
C++
448 lines
14 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "Common.h"
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#include "ArmEmitter.h"
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#include "CPUDetect.h"
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#include <assert.h>
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#include <stdarg.h>
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namespace ArmGen
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{
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void ARMXEmitter::SetCodePtr(u8 *ptr)
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{
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code = ptr;
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startcode = code;
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}
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const u8 *ARMXEmitter::GetCodePtr() const
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{
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return code;
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}
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u8 *ARMXEmitter::GetWritableCodePtr()
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{
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return code;
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}
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void ARMXEmitter::ReserveCodeSpace(u32 bytes)
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{
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for (u32 i = 0; i < bytes/4; i++)
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Write32(0xE1200070); //bkpt 0
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}
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const u8 *ARMXEmitter::AlignCode16()
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{
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ReserveCodeSpace((-(s32)code) & 15);
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return code;
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}
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const u8 *ARMXEmitter::AlignCodePage()
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{
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ReserveCodeSpace((-(s32)code) & 4095);
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return code;
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}
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void ARMXEmitter::Flush()
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{
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__builtin___clear_cache (startcode, code);
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SLEEP(0);
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}
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void ARMXEmitter::SetCC(CCFlags cond)
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{
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condition = cond << 28;
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}
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void ARMXEmitter::NOP(int count)
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{
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for (int i = 0; i < count; i++) {
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Write32(condition | 0x01A00000);
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}
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}
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void ARMXEmitter::SETEND(bool BE)
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{
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//SETEND is non-conditional
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Write32( 0xF1010000 | (BE << 9));
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}
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void ARMXEmitter::BKPT(u16 arg)
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{
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Write32(condition | 0x01200070 | (arg << 4 & 0x000FFF00) | (arg & 0x0000000F));
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}
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void ARMXEmitter::YIELD()
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{
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Write32(condition | 0x0320F001);
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}
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FixupBranch ARMXEmitter::B()
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{
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FixupBranch branch;
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branch.type = 0; // Zero for B
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branch.ptr = code;
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branch.condition = condition;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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FixupBranch ARMXEmitter::BL()
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{
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FixupBranch branch;
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branch.type = 1; // Zero for B
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branch.ptr = code;
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branch.condition = condition;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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FixupBranch ARMXEmitter::B_CC(CCFlags Cond)
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{
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FixupBranch branch;
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branch.type = 0; // Zero for B
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branch.ptr = code;
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branch.condition = Cond << 28;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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void ARMXEmitter::B_CC(CCFlags Cond, const void *fnptr)
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{
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s32 distance = (s32)fnptr - (s32(code) + 8);
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"B_CC out of range (%p calls %p)", code, fnptr);
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Write32((Cond << 28) | 0x0A000000 | ((distance >> 2) & 0x00FFFFFF));
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}
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FixupBranch ARMXEmitter::BL_CC(CCFlags Cond)
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{
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FixupBranch branch;
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branch.type = 1; // Zero for B
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branch.ptr = code;
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branch.condition = Cond << 28;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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void ARMXEmitter::SetJumpTarget(FixupBranch const &branch)
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{
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s32 distance = (s32(code) - 8) - (s32)branch.ptr;
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"SetJumpTarget out of range (%p calls %p)", code,
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branch.ptr);
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if(branch.type == 0) // B
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*(u32*)branch.ptr = (u32)(branch.condition | (10 << 24) | ((distance >> 2) &
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0x00FFFFFF));
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else // BL
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*(u32*)branch.ptr = (u32)(branch.condition | 0x0B000000 | ((distance >> 2)
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& 0x00FFFFFF));
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}
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void ARMXEmitter::B (const void *fnptr)
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{
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s32 distance = (s32)fnptr - (s32(code) + 8);
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"B out of range (%p calls %p)", code, fnptr);
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Write32(condition | 0x0A000000 | ((distance >> 2) & 0x00FFFFFF));
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}
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void ARMXEmitter::B(ARMReg src)
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{
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Write32(condition | (18 << 20) | (0xFFF << 8) | (1 << 4) | src);
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}
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void ARMXEmitter::BL(const void *fnptr)
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{
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s32 distance = (s32)fnptr - (s32(code) + 8);
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"BL out of range (%p calls %p)", code, fnptr);
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Write32(condition | 0x0B000000 | ((distance >> 2) & 0x00FFFFFF));
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}
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void ARMXEmitter::BL(ARMReg src)
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{
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Write32(condition | 0x12FFF30 | src);
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}
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void ARMXEmitter::PUSH(const int num, ...)
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{
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u16 RegList = 0;
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u8 Reg;
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int i;
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va_list vl;
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va_start(vl, num);
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for (i=0;i<num;i++)
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{
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Reg = va_arg(vl, u32);
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RegList |= (1 << Reg);
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}
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va_end(vl);
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Write32(condition | (2349 << 16) | RegList);
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}
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void ARMXEmitter::POP(const int num, ...)
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{
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u16 RegList = 0;
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u8 Reg;
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int i;
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va_list vl;
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va_start(vl, num);
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for (i=0;i<num;i++)
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{
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Reg = va_arg(vl, u32);
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RegList |= (1 << Reg);
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}
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va_end(vl);
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Write32(condition | (2237 << 16) | RegList);
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}
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void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2)
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{
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Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | op2.Imm5() | (op << 4) | src);
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}
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void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, ARMReg op2)
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{
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Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | (op2 << 8) | (op << 4) | src);
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}
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// IMM, REG, IMMSREG, RSR
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// -1 for invalid if the instruction doesn't support that
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const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s)
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{17, 1, 1, 1}, // EOR(s)
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{18, 2, 2, 2}, // SUB(s)
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{19, 3, 3, 3}, // RSB(s)
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{20, 4, 4, 4}, // ADD(s)
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{21, 5, 5, 5}, // ADC(s)
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{22, 6, 6, 6}, // SBC(s)
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{23, 7, 7, 7}, // RSC(s)
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{24, 8, 8, 8}, // TST
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{25, 9, 9, 9}, // TEQ
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{26, 10, 10, 10}, // CMP
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{27, 11, 11, 11}, // CMN
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{28, 12, 12, 12}, // ORR(s)
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{29, 13, 13, 13}, // MOV(s)
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{30, 14, 14, 14}, // BIC(s)
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{31, 15, 15, 15}, // MVN(s)
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{24, -1, -1, -1}, // MOVW
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{26, -1, -1, -1}, // MOVT
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};
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const char *InstNames[] = { "AND",
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"EOR",
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"SUB",
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"RSB",
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"ADD",
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"ADC",
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"SBC",
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"RSC",
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"TST",
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"TEQ",
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"CMP",
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"CMN",
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"ORR",
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"MOV",
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"BIC",
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"MVN"
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};
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void ARMXEmitter::AND (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm); }
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void ARMXEmitter::ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm, true); }
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void ARMXEmitter::EOR (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(1, Rd, Rn, Rm); }
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void ARMXEmitter::EORS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(1, Rd, Rn, Rm, true); }
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void ARMXEmitter::SUB (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(2, Rd, Rn, Rm); }
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void ARMXEmitter::SUBS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(2, Rd, Rn, Rm, true); }
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void ARMXEmitter::RSB (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(3, Rd, Rn, Rm); }
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void ARMXEmitter::RSBS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(3, Rd, Rn, Rm, true); }
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void ARMXEmitter::ADD (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(4, Rd, Rn, Rm); }
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void ARMXEmitter::ADDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(4, Rd, Rn, Rm, true); }
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void ARMXEmitter::ADC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(5, Rd, Rn, Rm); }
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void ARMXEmitter::ADCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(5, Rd, Rn, Rm, true); }
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void ARMXEmitter::SBC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(6, Rd, Rn, Rm); }
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void ARMXEmitter::SBCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(6, Rd, Rn, Rm, true); }
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void ARMXEmitter::RSC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(7, Rd, Rn, Rm); }
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void ARMXEmitter::RSCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(7, Rd, Rn, Rm, true); }
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void ARMXEmitter::TST ( ARMReg Rn, Operand2 Rm) { WriteInstruction(8, R0, Rn, Rm, true); }
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void ARMXEmitter::TEQ ( ARMReg Rn, Operand2 Rm) { WriteInstruction(9, R0, Rn, Rm, true); }
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void ARMXEmitter::CMP ( ARMReg Rn, Operand2 Rm) { WriteInstruction(10, R0, Rn, Rm, true); }
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void ARMXEmitter::CMN ( ARMReg Rn, Operand2 Rm) { WriteInstruction(11, R0, Rn, Rm, true); }
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void ARMXEmitter::ORR (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(12, Rd, Rn, Rm); }
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void ARMXEmitter::ORRS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(12, Rd, Rn, Rm, true); }
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void ARMXEmitter::MOV (ARMReg Rd, Operand2 Rm) { WriteInstruction(13, Rd, R0, Rm); }
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void ARMXEmitter::MOVS(ARMReg Rd, Operand2 Rm) { WriteInstruction(13, Rd, R0, Rm, true); }
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void ARMXEmitter::BIC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(14, Rd, Rn, Rm); }
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void ARMXEmitter::BICS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(14, Rd, Rn, Rm, true); }
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void ARMXEmitter::MVN (ARMReg Rd, Operand2 Rm) { WriteInstruction(15, Rd, R0, Rm); }
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void ARMXEmitter::MVNS(ARMReg Rd, Operand2 Rm) { WriteInstruction(15, Rd, R0, Rm, true); }
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void ARMXEmitter::MOVW(ARMReg Rd, Operand2 Rm) { WriteInstruction(16, Rd, R0, Rm); }
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void ARMXEmitter::MOVT(ARMReg Rd, Operand2 Rm, bool TopBits) { WriteInstruction(17, Rd, R0, TopBits ? Rm.Value >> 16 : Rm); }
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void ARMXEmitter::WriteInstruction (u32 Op, ARMReg Rd, ARMReg Rn, Operand2 Rm, bool SetFlags) // This can get renamed later
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{
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u32 op = InstOps[Op][Rm.GetType()]; // Type always decided by last operand
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u32 Data = Rm.GetData();
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if (Rm.GetType() == TYPE_IMM)
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{
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switch (Op)
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{
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// MOV cases that support IMM16
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case 16:
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case 17:
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Data = Rm.Imm16();
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break;
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default:
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break;
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}
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}
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if (op == -1)
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_assert_msg_(DYNA_REC, false, "%s not yet support %d", InstNames[Op], Rm.GetType());
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Write32(condition | (op << 21) | (SetFlags ? (1 << 20) : 0) | Rn << 16 | Rd << 12 | Data);
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}
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// Data Operations
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void ARMXEmitter::LSL (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, false, dest, src, op2);}
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void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, true, dest, src, op2);}
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void ARMXEmitter::LSL (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, false, dest, src, op2);}
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void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, true, dest, src, op2);}
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void ARMXEmitter::MUL (ARMReg dest, ARMReg src, ARMReg op2)
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{
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Write32(condition | (dest << 16) | (src << 8) | (9 << 4) | op2);
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}
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void ARMXEmitter::MULS(ARMReg dest, ARMReg src, ARMReg op2)
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{
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Write32(condition | (1 << 20) | (dest << 16) | (src << 8) | (9 << 4) | op2);
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}
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void ARMXEmitter::SXTB (ARMReg dest, ARMReg op2)
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{
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Write32(condition | (0x6AF << 16) | (dest << 12) | (7 << 4) | op2);
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}
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void ARMXEmitter::SXTH (ARMReg dest, ARMReg op2, u8 rotation)
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{
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SXTAH(dest, (ARMReg)15, op2, rotation);
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}
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void ARMXEmitter::SXTAH(ARMReg dest, ARMReg src, ARMReg op2, u8 rotation)
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{
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// bits ten and 11 are the rotation amount, see 8.8.232 for more
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// information
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Write32(condition | (0x6B << 20) | (src << 16) | (dest << 12) | (rotation << 10) | (7 << 4) | op2);
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}
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void ARMXEmitter::REV (ARMReg dest, ARMReg src )
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{
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Write32(condition | (107 << 20) | (15 << 16) | (dest << 12) | (243 << 4) | src);
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}
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void ARMXEmitter::_MSR (bool nzcvq, bool g, Operand2 op2)
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{
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Write32(condition | (0x320F << 12) | (nzcvq << 19) | (g << 18) | op2.Imm12Mod());
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}
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void ARMXEmitter::_MSR (bool nzcvq, bool g, ARMReg src)
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{
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Write32(condition | (0x120F << 12) | (nzcvq << 19) | (g << 18) | src);
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}
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void ARMXEmitter::MRS (ARMReg dest)
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{
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Write32(condition | (16 << 20) | (15 << 16) | (dest << 12));
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}
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void ARMXEmitter::WriteStoreOp(u32 op, ARMReg dest, ARMReg src, Operand2 op2)
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{
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if (op2.GetData() == 0) // Don't index
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Write32(condition | (op << 20) | (dest << 16) | (src << 12) | op2.Imm12());
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else
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Write32(condition | (op << 20) | (3 << 23) | (dest << 16) | (src << 12) | op2.Imm12());
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}
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void ARMXEmitter::STR (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x40, dest, src, op);}
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void ARMXEmitter::STRB(ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x44, dest, src, op);}
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void ARMXEmitter::STR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
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{
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Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | offset);
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}
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void ARMXEmitter::LDREX(ARMReg dest, ARMReg base)
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{
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Write32(condition | (25 << 20) | (base << 16) | (dest << 12) | 0xF9F);
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}
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void ARMXEmitter::STREX(ARMReg dest, ARMReg base, ARMReg op)
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{
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_assert_msg_(DYNA_REC, (dest != base && dest != op), "STREX dest can't be other two registers");
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Write32(condition | (24 << 20) | (base << 16) | (dest << 12) | (0xF9 << 4) | op);
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}
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void ARMXEmitter::DMB ()
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{
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Write32(0xF57FF05E);
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}
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void ARMXEmitter::LDR (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x41, src, dest, op);}
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void ARMXEmitter::LDRB(ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x45, src, dest, op);}
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void ARMXEmitter::LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index,
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bool Add)
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{
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Write32(condition | (0x61 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | offset);
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}
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void ARMXEmitter::WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList)
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{
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Write32(condition | (op << 20) | (WriteBack << 21) | (dest << 16) | RegList);
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}
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void ARMXEmitter::STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...)
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{
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u16 RegList = 0;
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u8 Reg;
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int i;
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va_list vl;
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va_start(vl, Regnum);
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|
for (i=0;i<Regnum;i++)
|
|
{
|
|
Reg = va_arg(vl, u32);
|
|
RegList |= (1 << Reg);
|
|
}
|
|
va_end(vl);
|
|
WriteRegStoreOp(0x90, dest, WriteBack, RegList);
|
|
}
|
|
void ARMXEmitter::LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...)
|
|
{
|
|
u16 RegList = 0;
|
|
u8 Reg;
|
|
int i;
|
|
va_list vl;
|
|
va_start(vl, Regnum);
|
|
for (i=0;i<Regnum;i++)
|
|
{
|
|
Reg = va_arg(vl, u32);
|
|
RegList |= (1 << Reg);
|
|
}
|
|
va_end(vl);
|
|
WriteRegStoreOp(0x89, dest, WriteBack, RegList);
|
|
}
|
|
// helper routines for setting pointers
|
|
void ARMXEmitter::CallCdeclFunction3(void* fnptr, u32 arg0, u32 arg1, u32 arg2)
|
|
{
|
|
}
|
|
|
|
void ARMXEmitter::CallCdeclFunction4(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3)
|
|
{
|
|
}
|
|
|
|
void ARMXEmitter::CallCdeclFunction5(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4)
|
|
{
|
|
}
|
|
|
|
void ARMXEmitter::CallCdeclFunction6(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5)
|
|
{
|
|
}
|
|
}
|