mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-11-24 22:10:01 +00:00
389 lines
8.9 KiB
C++
389 lines
8.9 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <cmath>
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#include "math/math_util.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Common/CPUDetect.h"
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#include "Core/Config.h"
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#include "Core/Reporting.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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namespace MIPSComp {
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void IRJit::Comp_VPFX(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int data = op & 0xFFFFF;
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int regnum = (op >> 24) & 3;
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switch (regnum) {
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case 0: // S
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js.prefixS = data;
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js.prefixSFlag = JitState::PREFIX_KNOWN_DIRTY;
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break;
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case 1: // T
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js.prefixT = data;
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js.prefixTFlag = JitState::PREFIX_KNOWN_DIRTY;
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break;
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case 2: // D
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js.prefixD = data;
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js.prefixDFlag = JitState::PREFIX_KNOWN_DIRTY;
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break;
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default:
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ERROR_LOG(CPU, "VPFX - bad regnum %i : data=%08x", regnum, data);
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break;
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}
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}
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void IRJit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) {
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if (prefix == 0xE4)
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return;
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int n = GetNumVectorElements(sz);
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u8 origV[4];
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static const float constantArray[8] = { 0.f, 1.f, 2.f, 0.5f, 3.f, 1.f / 3.f, 0.25f, 1.f / 6.f };
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for (int i = 0; i < n; i++)
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origV[i] = vregs[i];
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for (int i = 0; i < n; i++) {
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int regnum = (prefix >> (i * 2)) & 3;
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int abs = (prefix >> (8 + i)) & 1;
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int negate = (prefix >> (16 + i)) & 1;
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int constants = (prefix >> (12 + i)) & 1;
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// Unchanged, hurray.
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if (!constants && regnum == i && !abs && !negate)
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continue;
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/*
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// This puts the value into a temp reg, so we won't write the modified value back.
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vregs[i] = fpr.GetTempV();
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if (!constants) {
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fpr.MapDirtyInV(vregs[i], origV[regnum]);
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fpr.SpillLockV(vregs[i]);
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// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
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// TODO: But some ops seem to use const 0 instead?
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if (regnum >= n) {
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WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(GetCompilerPC()));
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regnum = 0;
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}
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if (abs) {
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fp.FABS(fpr.V(vregs[i]), fpr.V(origV[regnum]));
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if (negate)
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fp.FNEG(fpr.V(vregs[i]), fpr.V(vregs[i]));
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} else {
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if (negate)
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fp.FNEG(fpr.V(vregs[i]), fpr.V(origV[regnum]));
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else
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fp.FMOV(fpr.V(vregs[i]), fpr.V(origV[regnum]));
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}
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} else {
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fpr.MapRegV(vregs[i], MAP_DIRTY | MAP_NOINIT);
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fpr.SpillLockV(vregs[i]);
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fp.MOVI2F(fpr.V(vregs[i]), constantArray[regnum + (abs << 2)], SCRATCH1, (bool)negate);
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}
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*/
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}
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}
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void IRJit::GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg) {
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_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
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GetVectorRegs(regs, sz, vectorReg);
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if (js.prefixD == 0)
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return;
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int n = GetNumVectorElements(sz);
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for (int i = 0; i < n; i++) {
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// Hopefully this is rare, we'll just write it into a reg we drop.
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//if (js.VfpuWriteMask(i))
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// regs[i] = fpr.GetTempV();
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}
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}
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void IRJit::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
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_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
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if (!js.prefixD)
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return;
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/*
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int n = GetNumVectorElements(sz);
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for (int i = 0; i < n; i++) {
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if (js.VfpuWriteMask(i))
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continue;
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int sat = (js.prefixD >> (i * 2)) & 3;
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if (sat == 1) {
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// clamped = x < 0 ? (x > 1 ? 1 : x) : x [0, 1]
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fpr.MapRegV(vregs[i], MAP_DIRTY);
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fp.MOVI2F(S0, 0.0f, SCRATCH1);
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fp.MOVI2F(S1, 1.0f, SCRATCH1);
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fp.FMIN(fpr.V(vregs[i]), fpr.V(vregs[i]), S1);
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fp.FMAX(fpr.V(vregs[i]), fpr.V(vregs[i]), S0);
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} else if (sat == 3) {
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// clamped = x < -1 ? (x > 1 ? 1 : x) : x [-1, 1]
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fpr.MapRegV(vregs[i], MAP_DIRTY);
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fp.MOVI2F(S0, -1.0f, SCRATCH1);
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fp.MOVI2F(S1, 1.0f, SCRATCH1);
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fp.FMIN(fpr.V(vregs[i]), fpr.V(vregs[i]), S1);
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fp.FMAX(fpr.V(vregs[i]), fpr.V(vregs[i]), S0);
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}
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}
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*/
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}
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void IRJit::Comp_SV(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_SVQ(MIPSOpcode op) {
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int imm = (signed short)(op & 0xFFFC);
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int vt = (((op >> 16) & 0x1f)) | ((op & 1) << 5);
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MIPSGPReg rs = _RS;
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u8 vregs[4];
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GetVectorRegs(vregs, V_Quad, vt);
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switch (op >> 26) {
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case 54: //lv.q
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{
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// TODO: Add vector load/store instruction to the IR
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ir.Write(IROp::LoadFloatV, vregs[0], rs, ir.AddConstant(imm));
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ir.Write(IROp::LoadFloatV, vregs[1], rs, ir.AddConstant(imm + 4));
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ir.Write(IROp::LoadFloatV, vregs[2], rs, ir.AddConstant(imm + 8));
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ir.Write(IROp::LoadFloatV, vregs[3], rs, ir.AddConstant(imm + 12));
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}
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break;
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case 62: //sv.q
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{
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// CC might be set by slow path below, so load regs first.
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ir.Write(IROp::StoreFloatV, vregs[0], rs, ir.AddConstant(imm));
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ir.Write(IROp::StoreFloatV, vregs[1], rs, ir.AddConstant(imm + 4));
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ir.Write(IROp::StoreFloatV, vregs[2], rs, ir.AddConstant(imm + 8));
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ir.Write(IROp::StoreFloatV, vregs[3], rs, ir.AddConstant(imm + 12));
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}
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break;
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default:
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DISABLE;
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break;
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}
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}
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void IRJit::Comp_VVectorInit(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VIdt(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VMatrixInit(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VHdp(MIPSOpcode op) {
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DISABLE;
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}
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static const float MEMORY_ALIGNED16(vavg_table[4]) = { 1.0f, 1.0f / 2.0f, 1.0f / 3.0f, 1.0f / 4.0f };
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void IRJit::Comp_Vhoriz(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VDot(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VecDo3(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VV2Op(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Pre-processing: Eliminate silly no-op VMOVs, common in Wipeout Pure
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if (((op >> 16) & 0x1f) == 0 && _VS == _VD && js.HasNoPrefix()) {
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return;
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}
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DISABLE;
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}
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void IRJit::Comp_Vi2f(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vh2f(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vf2i(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Mftv(MIPSOpcode op) {
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int imm = op & 0xFF;
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MIPSGPReg rt = _RT;
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switch ((op >> 21) & 0x1f) {
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case 3: //mfv / mfvc
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// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.
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if (rt != 0) {
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if (imm < 128) { //R(rt) = VI(imm);
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ir.Write(IROp::VMovToGPR, rt, imm);
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logBlocks = 1;
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} else {
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DISABLE;
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}
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}
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break;
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case 7: // mtv
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if (imm < 128) {
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ir.Write(IROp::VMovFromGPR, imm, rt);
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logBlocks = 1;
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} else {
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DISABLE;
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}
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break;
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default:
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DISABLE;
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}
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}
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void IRJit::Comp_Vmfvc(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vmtvc(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vmmov(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VScl(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vmmul(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vmscl(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vtfm(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VCrs(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VDet(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vi2x(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vx2i(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_VCrossQuat(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vcmp(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vcmov(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Viim(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vfim(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vcst(MIPSOpcode op) {
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DISABLE;
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}
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// Very heavily used by FF:CC. Should be replaced by a fast approximation instead of
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// calling the math library.
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void IRJit::Comp_VRot(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vsgn(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vocp(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_ColorConv(MIPSOpcode op) {
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DISABLE;
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}
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void IRJit::Comp_Vbfy(MIPSOpcode op) {
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DISABLE;
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}
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}
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