mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-11-23 21:39:52 +00:00
454 lines
12 KiB
C++
454 lines
12 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Core/Config.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/ARM/ArmJit.h"
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#include "Core/MIPS/ARM/ArmRegCache.h"
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#include "Common/CPUDetect.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp
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{
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using namespace ArmGen;
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using namespace ArmJitConstants;
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void ArmJit::Comp_FPU3op(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE(FPU);
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int ft = _FT;
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int fs = _FS;
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int fd = _FD;
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fpr.MapDirtyInIn(fd, fs, ft);
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switch (op & 0x3f)
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{
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case 0: VADD(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add
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case 1: VSUB(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: { //F(fd) = F(fs) * F(ft); //mul
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Optimization possible if destination is the same
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if (fd == (int)((nextOp>>6) & 0x1F)) {
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// VMUL + VNEG -> VNMUL
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if (!strcmp(MIPSGetName(nextOp), "neg.s")) {
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if (fd == (int)((nextOp>>11) & 0x1F)) {
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VNMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft));
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EatInstruction(nextOp);
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}
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return;
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}
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}
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VMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft));
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break;
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}
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case 3: VDIV(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) / F(ft); //div
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default:
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DISABLE;
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return;
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}
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}
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extern int logBlocks;
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void ArmJit::Comp_FPULS(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE(LSU_FPU);
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CheckMemoryBreakpoint();
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s32 offset = (s16)(op & 0xFFFF);
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int ft = _FT;
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MIPSGPReg rs = _RS;
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// u32 addr = R(rs) + offset;
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// logBlocks = 1;
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bool doCheck = false;
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switch(op >> 26)
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{
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case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
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if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) {
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gpr.MapRegAsPointer(rs);
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fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
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VLDR(fpr.R(ft), gpr.RPtr(rs), offset);
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break;
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}
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fpr.SpillLock(ft);
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fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
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if (gpr.IsImm(rs)) {
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u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
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gpr.SetRegImm(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, offset);
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} else {
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SetCCAndR0ForSafeAddress(rs, offset, SCRATCHREG2);
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doCheck = true;
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}
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ADD(R0, R0, MEMBASEREG);
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}
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#ifdef __ARM_ARCH_7S__
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FixupBranch skip;
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if (doCheck) {
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skip = B_CC(CC_EQ);
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}
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VLDR(fpr.R(ft), R0, 0);
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if (doCheck) {
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SetJumpTarget(skip);
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}
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#else
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VLDR(fpr.R(ft), R0, 0);
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if (doCheck) {
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SetCC(CC_EQ);
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MOVI2R(R0, 0);
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VMOV(fpr.R(ft), R0);
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SetCC(CC_AL);
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}
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#endif
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fpr.ReleaseSpillLocksAndDiscardTemps();
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break;
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case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
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if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) {
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gpr.MapRegAsPointer(rs);
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fpr.MapReg(ft, 0);
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VSTR(fpr.R(ft), gpr.RPtr(rs), offset);
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break;
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}
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fpr.MapReg(ft);
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if (gpr.IsImm(rs)) {
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u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
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gpr.SetRegImm(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, offset);
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} else {
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SetCCAndR0ForSafeAddress(rs, offset, SCRATCHREG2);
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doCheck = true;
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}
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ADD(R0, R0, MEMBASEREG);
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}
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#ifdef __ARM_ARCH_7S__
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FixupBranch skip2;
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if (doCheck) {
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skip2 = B_CC(CC_EQ);
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}
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VSTR(fpr.R(ft), R0, 0);
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if (doCheck) {
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SetJumpTarget(skip2);
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}
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#else
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VSTR(fpr.R(ft), R0, 0);
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if (doCheck) {
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SetCC(CC_AL);
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}
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#endif
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void ArmJit::Comp_FPUComp(MIPSOpcode op) {
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CONDITIONAL_DISABLE(FPU_COMP);
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int opc = op & 0xF;
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if (opc >= 8) opc -= 8; // alias
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if (opc == 0) { // f, sf (signalling false)
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gpr.SetImm(MIPS_REG_FPCOND, 0);
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return;
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}
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int fs = _FS;
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int ft = _FT;
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gpr.MapReg(MIPS_REG_FPCOND, MAP_DIRTY | MAP_NOINIT);
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fpr.MapInIn(fs, ft);
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VCMP(fpr.R(fs), fpr.R(ft));
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VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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switch(opc)
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{
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case 1: // un, ngle (unordered)
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SetCC(CC_VS);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_VC);
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break;
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case 2: // eq, seq (equal, ordered)
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SetCC(CC_EQ);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_NEQ);
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break;
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case 3: // ueq, ngl (equal, unordered)
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SetCC(CC_EQ);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_NEQ);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 0);
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SetCC(CC_VS);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_AL);
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return;
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case 4: // olt, lt (less than, ordered)
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SetCC(CC_LO);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_HS);
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break;
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case 5: // ult, nge (less than, unordered)
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SetCC(CC_LT);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_GE);
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break;
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case 6: // ole, le (less equal, ordered)
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SetCC(CC_LS);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_HI);
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break;
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case 7: // ule, ngt (less equal, unordered)
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SetCC(CC_LE);
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 1);
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SetCC(CC_GT);
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break;
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default:
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Comp_Generic(op);
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return;
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}
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MOVI2R(gpr.R(MIPS_REG_FPCOND), 0);
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SetCC(CC_AL);
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}
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void ArmJit::Comp_FPU2op(MIPSOpcode op) {
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CONDITIONAL_DISABLE(FPU);
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int fs = _FS;
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int fd = _FD;
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switch (op & 0x3f) {
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case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
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fpr.MapDirtyIn(fd, fs);
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VSQRT(fpr.R(fd), fpr.R(fs));
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break;
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case 5: //F(fd) = fabsf(F(fs)); break; //abs
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fpr.MapDirtyIn(fd, fs);
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VABS(fpr.R(fd), fpr.R(fs));
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break;
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case 6: //F(fd) = F(fs); break; //mov
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fpr.MapDirtyIn(fd, fs);
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VMOV(fpr.R(fd), fpr.R(fs));
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break;
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case 7: //F(fd) = -F(fs); break; //neg
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fpr.MapDirtyIn(fd, fs);
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VNEG(fpr.R(fd), fpr.R(fs));
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break;
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case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
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RestoreRoundingMode();
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fpr.MapDirtyIn(fd, fs);
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED);
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break;
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case 13: //FsI(fd) = Rto0(F(fs))); break; //trunc.w.s
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fpr.MapDirtyIn(fd, fs);
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VCMP(fpr.R(fs), fpr.R(fs));
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED | ROUND_TO_ZERO);
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VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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SetCC(CC_VS);
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MOVIU2F(fpr.R(fd), 0x7FFFFFFF, SCRATCHREG1);
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SetCC(CC_AL);
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break;
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case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
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{
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RestoreRoundingMode();
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fpr.MapDirtyIn(fd, fs);
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VMRS(SCRATCHREG2);
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// Assume we're always in round-to-nearest mode.
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ORR(SCRATCHREG1, SCRATCHREG2, AssumeMakeOperand2(1 << 22));
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VMSR(SCRATCHREG1);
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VCMP(fpr.R(fs), fpr.R(fs));
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED);
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VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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SetCC(CC_VS);
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MOVIU2F(fpr.R(fd), 0x7FFFFFFF, SCRATCHREG1);
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SetCC(CC_AL);
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// Set the rounding mode back. TODO: Keep it? Dirty?
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VMSR(SCRATCHREG2);
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break;
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}
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case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
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{
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RestoreRoundingMode();
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fpr.MapDirtyIn(fd, fs);
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VMRS(SCRATCHREG2);
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// Assume we're always in round-to-nearest mode.
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ORR(SCRATCHREG1, SCRATCHREG2, AssumeMakeOperand2(2 << 22));
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VMSR(SCRATCHREG1);
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VCMP(fpr.R(fs), fpr.R(fs));
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED);
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VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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SetCC(CC_VS);
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MOVIU2F(fpr.R(fd), 0x7FFFFFFF, SCRATCHREG1);
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SetCC(CC_AL);
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// Set the rounding mode back. TODO: Keep it? Dirty?
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VMSR(SCRATCHREG2);
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break;
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}
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case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
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fpr.MapDirtyIn(fd, fs);
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VCVT(fpr.R(fd), fpr.R(fs), TO_FLOAT | IS_SIGNED);
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break;
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case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
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fpr.MapDirtyIn(fd, fs);
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VCMP(fpr.R(fs), fpr.R(fs));
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED);
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VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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SetCC(CC_VS);
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MOVIU2F(fpr.R(fd), 0x7FFFFFFF, SCRATCHREG1);
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SetCC(CC_AL);
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break;
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default:
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DISABLE;
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}
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}
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void ArmJit::Comp_mxc1(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE(FPU_XFER);
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int fs = _FS;
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MIPSGPReg rt = _RT;
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switch ((op >> 21) & 0x1f)
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{
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case 0: // R(rt) = FI(fs); break; //mfc1
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if (rt == MIPS_REG_ZERO) {
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return;
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}
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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if (fpr.IsMapped(fs)) {
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VMOV(gpr.R(rt), fpr.R(fs));
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} else {
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LDR(gpr.R(rt), CTXREG, fpr.GetMipsRegOffset(fs));
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}
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return;
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case 2: //cfc1
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if (rt == MIPS_REG_ZERO) {
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return;
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}
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if (fs == 31) {
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if (gpr.IsImm(MIPS_REG_FPCOND)) {
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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if (gpr.GetImm(MIPS_REG_FPCOND) & 1) {
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ORI2R(gpr.R(rt), gpr.R(rt), 0x1 << 23, SCRATCHREG2);
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} else {
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ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), SCRATCHREG2);
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}
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} else {
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gpr.MapDirtyIn(rt, MIPS_REG_FPCOND);
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LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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#if PPSSPP_ARCH(ARMV7)
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BFI(gpr.R(rt), gpr.R(MIPS_REG_FPCOND), 23, 1);
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#else
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AND(SCRATCHREG1, gpr.R(MIPS_REG_FPCOND), Operand2(1)); // Just in case
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ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), SCRATCHREG2); // SCRATCHREG2 won't be used, this turns into a simple BIC.
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ORR(gpr.R(rt), gpr.R(rt), Operand2(SCRATCHREG1, ST_LSL, 23));
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#endif
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}
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} else if (fs == 0) {
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gpr.SetImm(rt, MIPSState::FCR0_VALUE);
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} else {
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// Unsupported regs are always 0.
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gpr.SetImm(rt, 0);
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}
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return;
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case 4: //FI(fs) = R(rt); break; //mtc1
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if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0) {
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fpr.MapReg(fs, MAP_NOINIT);
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MOVI2F(fpr.R(fs), 0.0f, R0);
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} else {
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gpr.MapReg(rt);
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fpr.MapReg(fs, MAP_NOINIT);
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VMOV(fpr.R(fs), gpr.R(rt));
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}
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return;
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case 6: //ctc1
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if (fs == 31) {
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// Must clear before setting, since ApplyRoundingMode() assumes it was cleared.
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RestoreRoundingMode();
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bool wasImm = gpr.IsImm(rt);
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u32 immVal = -1;
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if (wasImm) {
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immVal = gpr.GetImm(rt);
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gpr.SetImm(MIPS_REG_FPCOND, (immVal >> 23) & 1);
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gpr.MapReg(rt);
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} else {
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gpr.MapDirtyIn(MIPS_REG_FPCOND, rt);
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}
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// Update MIPS state
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// TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg?
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STR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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if (!wasImm) {
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#if PPSSPP_ARCH(ARMV7)
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UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);
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#else
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MOV(SCRATCHREG1, Operand2(gpr.R(rt), ST_LSR, 23));
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AND(gpr.R(MIPS_REG_FPCOND), SCRATCHREG1, Operand2(1));
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#endif
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UpdateRoundingMode();
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} else {
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UpdateRoundingMode(immVal);
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|
}
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ApplyRoundingMode();
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} else {
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Comp_Generic(op);
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}
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return;
|
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}
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}
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|
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} // namespace MIPSComp
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#endif // PPSSPP_ARCH(ARM)
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