mirror of
https://github.com/hrydgard/ppsspp.git
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262 lines
6.6 KiB
C++
262 lines
6.6 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "../../MemMap.h"
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#include "../MIPSAnalyst.h"
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#include "../../Config.h"
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#include "Jit.h"
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#include "RegCache.h"
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE Comp_Generic(op); return;
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#define CONDITIONAL_DISABLE ;
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#define DISABLE Comp_Generic(op); return;
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namespace MIPSComp
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{
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void Jit::CompITypeMemRead(u32 op, u32 bits, void *func)
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{
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op&0xFFFF);
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int rt = _RT;
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int rs = _RS;
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gpr.Lock(rt, rs);
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gpr.BindToRegister(rt, rt == rs, true);
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if (gpr.R(rs).IsImm())
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{
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void *data = Memory::GetPointer(gpr.R(rs).GetImmValue() + offset);
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if (data)
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MOVZX(32, bits, gpr.RX(rt), M(data));
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else
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MOV(32, gpr.R(rt), Imm32(0));
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}
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else if (!g_Config.bFastMemory)
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{
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MOV(32, R(EAX), gpr.R(rs));
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// Is it in physical ram?
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CMP(32, R(EAX), Imm32(0x08000000));
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FixupBranch tooLow = J_CC(CC_L);
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CMP(32, R(EAX), Imm32(0x0A000000));
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FixupBranch tooHigh = J_CC(CC_GE);
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const u8* safe = GetCodePtr();
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#ifdef _M_IX86
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MOVZX(32, bits, gpr.RX(rt), MDisp(EAX, (u32)Memory::base + offset));
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#else
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MOVZX(32, bits, gpr.RX(rt), MComplex(RBX, EAX, SCALE_1, offset));
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#endif
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FixupBranch skip = J();
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SetJumpTarget(tooLow);
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SetJumpTarget(tooHigh);
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// Might also be the scratchpad.
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CMP(32, R(EAX), Imm32(0x00010000));
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FixupBranch tooLow2 = J_CC(CC_L);
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CMP(32, R(EAX), Imm32(0x00014000));
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J_CC(CC_L, safe);
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SetJumpTarget(tooLow2);
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ADD(32, R(EAX), Imm32(offset));
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ABI_CallFunctionA(thunks.ProtectFunction(func, 1), R(EAX));
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MOVZX(32, bits, gpr.RX(rt), R(EAX));
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SetJumpTarget(skip);
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}
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else
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{
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MOV(32, R(EAX), gpr.R(rs));
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#ifdef _M_IX86
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AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
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MOVZX(32, bits, gpr.RX(rt), MDisp(EAX, (u32)Memory::base + offset));
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#else
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MOVZX(32, bits, gpr.RX(rt), MComplex(RBX, EAX, SCALE_1, offset));
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#endif
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}
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gpr.UnlockAll();
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}
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void Jit::CompITypeMemWrite(u32 op, u32 bits, void *func)
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{
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op&0xFFFF);
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int rt = _RT;
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int rs = _RS;
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gpr.Lock(rt, rs);
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gpr.BindToRegister(rt, true, false);
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if (gpr.R(rs).IsImm())
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{
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void *data = Memory::GetPointer(gpr.R(rs).GetImmValue() + offset);
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if (data)
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MOV(bits, M(data), gpr.R(rt));
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else if (bits == 8)
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MOV(bits, M(data), Imm8(0));
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else if (bits == 16)
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MOV(bits, M(data), Imm16(0));
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else
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MOV(bits, M(data), Imm32(0));
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}
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else if (!g_Config.bFastMemory)
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{
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MOV(32, R(EAX), gpr.R(rs));
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// Is it in physical ram?
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CMP(32, R(EAX), Imm32(0x08000000));
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FixupBranch tooLow = J_CC(CC_L);
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CMP(32, R(EAX), Imm32(0x0A000000));
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FixupBranch tooHigh = J_CC(CC_GE);
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const u8* safe = GetCodePtr();
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#ifdef _M_IX86
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MOV(bits, MDisp(EAX, (u32)Memory::base + offset), gpr.R(rt));
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#else
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MOV(bits, MComplex(RBX, EAX, SCALE_1, offset), gpr.R(rt));
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#endif
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FixupBranch skip = J();
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SetJumpTarget(tooLow);
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SetJumpTarget(tooHigh);
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// Might also be the scratchpad.
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CMP(32, R(EAX), Imm32(0x00010000));
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FixupBranch tooLow2 = J_CC(CC_L);
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CMP(32, R(EAX), Imm32(0x00014000));
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J_CC(CC_L, safe);
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SetJumpTarget(tooLow2);
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ADD(32, R(EAX), Imm32(offset));
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ABI_CallFunctionAA(thunks.ProtectFunction(func, 2), gpr.R(rt), R(EAX));
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SetJumpTarget(skip);
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}
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else
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{
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MOV(32, R(EAX), gpr.R(rs));
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#ifdef _M_IX86
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AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
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MOV(bits, MDisp(EAX, (u32)Memory::base + offset), gpr.R(rt));
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#else
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MOV(bits, MComplex(RBX, EAX, SCALE_1, offset), gpr.R(rt));
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#endif
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}
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gpr.UnlockAll();
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}
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void Jit::Comp_ITypeMem(u32 op)
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{
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op&0xFFFF);
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int rt = _RT;
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int rs = _RS;
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int o = op>>26;
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if (((op >> 29) & 1) == 0 && rt == 0) {
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// Don't load anything into $zr
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return;
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}
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switch (o)
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{
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case 37: //R(rt) = ReadMem16(addr); break; //lhu
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CompITypeMemRead(op, 16, (void *) &Memory::Read_U16);
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break;
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case 36: //R(rt) = ReadMem8 (addr); break; //lbu
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CompITypeMemRead(op, 8, (void *) &Memory::Read_U8);
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break;
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case 35: //R(rt) = ReadMem32(addr); break; //lw
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CompITypeMemRead(op, 32, (void *) &Memory::Read_U16);
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break;
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case 132: //R(rt) = (u32)(s32)(s8) ReadMem8 (addr); break; //lb
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case 133: //R(rt) = (u32)(s32)(s16)ReadMem16(addr); break; //lh
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case 140: //WriteMem8 (addr, R(rt)); break; //sb
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Comp_Generic(op);
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return;
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case 41: //WriteMem16(addr, R(rt)); break; //sh
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CompITypeMemWrite(op, 16, (void *) &Memory::Write_U16);
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break;
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case 43: //WriteMem32(addr, R(rt)); break; //sw
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CompITypeMemWrite(op, 32, (void *) &Memory::Write_U32);
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break;
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case 134: //lwl
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{
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Crash();
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//u32 shift = (addr & 3) << 3;
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//u32 mem = ReadMem32(addr & 0xfffffffc);
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//R(rt) = ( u32(R(rt)) & (0x00ffffff >> shift) ) | ( mem << (24 - shift) );
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}
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break;
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case 138: //lwr
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{
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Crash();
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//u32 shift = (addr & 3) << 3;
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//u32 mem = ReadMem32(addr & 0xfffffffc);
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//R(rt) = ( u32(rt) & (0xffffff00 << (24 - shift)) ) | ( mem >> shift );
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}
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break;
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case 142: //swl
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{
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Crash();
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//u32 shift = (addr & 3) << 3;
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//u32 mem = ReadMem32(addr & 0xfffffffc);
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//WriteMem32((addr & 0xfffffffc), ( ( u32(R(rt)) >> (24 - shift) ) ) |
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// ( mem & (0xffffff00 << shift) ));
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}
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break;
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case 146: //swr
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{
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Crash();
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// u32 shift = (addr & 3) << 3;
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// u32 mem = ReadMem32(addr & 0xfffffffc);
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//
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// WriteMem32((addr & 0xfffffffc), ( ( u32(R(rt)) << shift ) |
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// (mem & (0x00ffffff >> (24 - shift)) ) ) );
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}
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break;
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default:
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Comp_Generic(op);
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return ;
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}
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}
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}
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