mirror of
https://github.com/hrydgard/ppsspp.git
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534 lines
14 KiB
C++
534 lines
14 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM64)
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#include <cstring>
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#include "base/logging.h"
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#include "Common/CPUDetect.h"
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#include "Core/Reporting.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/ARM64/Arm64RegCacheFPU.h"
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#include "Core/MIPS/ARM64/Arm64Jit.h"
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#include "Core/MIPS/MIPSTables.h"
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using namespace Arm64Gen;
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using namespace Arm64JitConstants;
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Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
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numARMFpuReg_ = 32;
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}
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void Arm64RegCacheFPU::Init(Arm64Gen::ARM64XEmitter *emit, Arm64Gen::ARM64FloatEmitter *fp) {
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emit_ = emit;
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fp_ = fp;
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}
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void Arm64RegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
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if (!initialReady) {
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SetupInitialRegs();
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initialReady = true;
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}
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memcpy(ar, arInitial, sizeof(ar));
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memcpy(mr, mrInitial, sizeof(mr));
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pendingFlush = false;
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}
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void Arm64RegCacheFPU::SetupInitialRegs() {
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for (int i = 0; i < numARMFpuReg_; i++) {
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arInitial[i].mipsReg = -1;
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arInitial[i].isDirty = false;
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}
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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mrInitial[i].loc = ML_MEM;
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mrInitial[i].reg = INVALID_REG;
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mrInitial[i].spillLock = false;
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mrInitial[i].tempLock = false;
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}
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}
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const ARM64Reg *Arm64RegCacheFPU::GetMIPSAllocationOrder(int &count) {
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// On ARM64, all 32 registers are fully 128-bit and fully interchangable so we don't
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// have to care about upper or lower registers. However, only S8-S15 are callee-save, and
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// only the bottom 64 bits of those. So we should allocate into these when we call
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// C functions, although we don't currently do so...
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static const ARM64Reg allocationOrder[] = {
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// Reserve four full 128-bit temp registers, should be plenty.
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S4, S5, S6, S7,
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S8, S9, S10, S11, // Partially callee-save (bottom 64 bits)
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S12, S13, S14, S15, // Partially callee-save (bottom 64 bits)
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S16, S17, S18, S19,
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S20, S21, S22, S23,
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S24, S25, S26, S27,
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S28, S29, S30, S31,
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};
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static const ARM64Reg allocationOrderNEONVFPU[] = {
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// Reserve four full 128-bit temp registers, should be plenty.
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// Then let's use 12 register as singles
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S4, S5, S6, S7,
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S8, S9, S10, S11,
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S12, S13, S14, S15,
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// And do quads in the rest? Or use a strategy more similar to what we do on x86?
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};
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if (jo_->useASIMDVFPU) {
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count = sizeof(allocationOrderNEONVFPU) / sizeof(const ARM64Reg);
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return allocationOrderNEONVFPU;
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} else {
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count = sizeof(allocationOrder) / sizeof(const ARM64Reg);
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return allocationOrder;
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}
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}
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bool Arm64RegCacheFPU::IsMapped(MIPSReg r) {
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return mr[r].loc == ML_ARMREG;
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}
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bool Arm64RegCacheFPU::IsInRAM(MIPSReg r) {
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return mr[r].loc == ML_MEM;
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}
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ARM64Reg Arm64RegCacheFPU::MapReg(MIPSReg mipsReg, int mapFlags) {
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// INFO_LOG(JIT, "FPR MapReg: %i flags=%i", mipsReg, mapFlags);
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if (jo_->useASIMDVFPU && mipsReg >= 32) {
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ERROR_LOG(JIT, "Cannot map VFPU registers to ARM VFP registers in NEON mode. PC=%08x", js_->compilerPC);
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return S0;
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}
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pendingFlush = true;
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// Let's see if it's already mapped. If so we just need to update the dirty flag.
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// We don't need to check for ML_NOINIT because we assume that anyone who maps
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// with that flag immediately writes a "known" value to the register.
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if (mr[mipsReg].loc == ML_ARMREG) {
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if (ar[mr[mipsReg].reg].mipsReg != mipsReg) {
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ERROR_LOG(JIT, "Reg mapping out of sync! MR %i", mipsReg);
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}
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if (mapFlags & MAP_DIRTY) {
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ar[mr[mipsReg].reg].isDirty = true;
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}
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//INFO_LOG(JIT, "Already mapped %i to %i", mipsReg, mr[mipsReg].reg);
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return (ARM64Reg)(mr[mipsReg].reg + S0);
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}
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// Okay, not mapped, so we need to allocate an ARM register.
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int allocCount;
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const ARM64Reg *allocOrder = GetMIPSAllocationOrder(allocCount);
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allocate:
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for (int i = 0; i < allocCount; i++) {
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int reg = DecodeReg(allocOrder[i]);
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if (ar[reg].mipsReg == -1) {
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// That means it's free. Grab it, and load the value into it (if requested).
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ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
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if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
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if (mr[mipsReg].loc == ML_MEM && mipsReg < TEMP0) {
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fp_->LDR(32, INDEX_UNSIGNED, (ARM64Reg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg));
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}
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}
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ar[reg].mipsReg = mipsReg;
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mr[mipsReg].loc = ML_ARMREG;
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mr[mipsReg].reg = reg;
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//INFO_LOG(JIT, "Mapped %i to %i", mipsReg, mr[mipsReg].reg);
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return (ARM64Reg)(reg + S0);
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}
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}
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// Still nothing. Let's spill a reg and goto 10.
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// TODO: Use age or something to choose which register to spill?
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// TODO: Spill dirty regs first? or opposite?
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int bestToSpill = -1;
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i] - S0;
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if (ar[reg].mipsReg != -1 && (mr[ar[reg].mipsReg].spillLock || mr[ar[reg].mipsReg].tempLock))
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continue;
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bestToSpill = reg;
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break;
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}
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if (bestToSpill != -1) {
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FlushArmReg((ARM64Reg)(S0 + bestToSpill));
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goto allocate;
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}
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// Uh oh, we have all them spilllocked....
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ERROR_LOG(JIT, "Out of spillable registers at PC %08x!!!", js_->compilerPC);
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return INVALID_REG;
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}
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void Arm64RegCacheFPU::MapInIn(MIPSReg rd, MIPSReg rs) {
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SpillLock(rd, rs);
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MapReg(rd);
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MapReg(rs);
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ReleaseSpillLock(rd);
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ReleaseSpillLock(rs);
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}
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void Arm64RegCacheFPU::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
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SpillLock(rd, rs);
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bool load = !avoidLoad || rd == rs;
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MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rs);
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ReleaseSpillLock(rd);
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ReleaseSpillLock(rs);
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}
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void Arm64RegCacheFPU::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
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SpillLock(rd, rs, rt);
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bool load = !avoidLoad || (rd == rs || rd == rt);
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MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLock(rd);
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ReleaseSpillLock(rs);
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ReleaseSpillLock(rt);
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}
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void Arm64RegCacheFPU::SpillLockV(const u8 *v, VectorSize sz) {
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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vr[v[i]].spillLock = true;
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}
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}
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void Arm64RegCacheFPU::SpillLockV(int vec, VectorSize sz) {
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u8 v[4];
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GetVectorRegs(v, sz, vec);
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SpillLockV(v, sz);
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}
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void Arm64RegCacheFPU::MapRegV(int vreg, int flags) {
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MapReg(vreg + 32, flags);
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}
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void Arm64RegCacheFPU::LoadToRegV(ARM64Reg armReg, int vreg) {
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if (vr[vreg].loc == ML_ARMREG) {
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fp_->FMOV(armReg, (ARM64Reg)(S0 + vr[vreg].reg));
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} else {
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MapRegV(vreg);
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fp_->FMOV(armReg, V(vreg));
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}
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}
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void Arm64RegCacheFPU::MapRegsAndSpillLockV(int vec, VectorSize sz, int flags) {
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u8 v[4];
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GetVectorRegs(v, sz, vec);
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SpillLockV(v, sz);
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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MapRegV(v[i], flags);
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}
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}
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void Arm64RegCacheFPU::MapRegsAndSpillLockV(const u8 *v, VectorSize sz, int flags) {
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SpillLockV(v, sz);
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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MapRegV(v[i], flags);
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}
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}
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void Arm64RegCacheFPU::MapInInV(int vs, int vt) {
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SpillLockV(vs);
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SpillLockV(vt);
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MapRegV(vs);
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MapRegV(vt);
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ReleaseSpillLockV(vs);
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ReleaseSpillLockV(vt);
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}
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void Arm64RegCacheFPU::MapDirtyInV(int vd, int vs, bool avoidLoad) {
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bool load = !avoidLoad || (vd == vs);
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SpillLockV(vd);
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SpillLockV(vs);
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MapRegV(vd, load ? MAP_DIRTY : MAP_NOINIT);
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MapRegV(vs);
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ReleaseSpillLockV(vd);
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ReleaseSpillLockV(vs);
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}
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void Arm64RegCacheFPU::MapDirtyInInV(int vd, int vs, int vt, bool avoidLoad) {
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bool load = !avoidLoad || (vd == vs || vd == vt);
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SpillLockV(vd);
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SpillLockV(vs);
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SpillLockV(vt);
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MapRegV(vd, load ? MAP_DIRTY : MAP_NOINIT);
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MapRegV(vs);
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MapRegV(vt);
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ReleaseSpillLockV(vd);
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ReleaseSpillLockV(vs);
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ReleaseSpillLockV(vt);
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}
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void Arm64RegCacheFPU::FlushArmReg(ARM64Reg r) {
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if (r >= S0 && r <= S31) {
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int reg = r - S0;
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if (ar[reg].mipsReg == -1) {
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// Nothing to do, reg not mapped.
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return;
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}
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if (ar[reg].mipsReg != -1) {
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if (ar[reg].isDirty && mr[ar[reg].mipsReg].loc == ML_ARMREG){
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//INFO_LOG(JIT, "Flushing ARM reg %i", reg);
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fp_->STR(32, INDEX_UNSIGNED, r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
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}
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// IMMs won't be in an ARM reg.
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mr[ar[reg].mipsReg].loc = ML_MEM;
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mr[ar[reg].mipsReg].reg = INVALID_REG;
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} else {
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ERROR_LOG(JIT, "Dirty but no mipsreg?");
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}
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ar[reg].mipsReg = -1;
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ar[reg].isDirty = false;
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}
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}
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void Arm64RegCacheFPU::FlushV(MIPSReg r) {
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FlushR(r + 32);
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}
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void Arm64RegCacheFPU::FlushR(MIPSReg r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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// IMM is not allowed for FP (yet).
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ERROR_LOG(JIT, "Imm in FP register?");
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break;
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case ML_ARMREG:
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if (mr[r].reg == INVALID_REG) {
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ERROR_LOG(JIT, "FlushR: MipsReg had bad ArmReg");
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}
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break;
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case ML_MEM:
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// Already there, nothing to do.
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break;
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default:
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//BAD
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break;
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}
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mr[r].loc = ML_MEM;
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mr[r].reg = (int)INVALID_REG;
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}
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Arm64Gen::ARM64Reg Arm64RegCacheFPU::ARM64RegForFlush(int r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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// IMM is not allowed for FP (yet).
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ERROR_LOG(JIT, "Imm in FP register?");
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return INVALID_REG;
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case ML_ARMREG:
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if (mr[r].reg == INVALID_REG) {
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ERROR_LOG_REPORT(JIT, "ARM64RegForFlush: MipsReg %d had bad ArmReg", r);
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return INVALID_REG;
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}
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// No need to flush if it's not dirty.
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if (!ar[mr[r].reg].isDirty) {
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return INVALID_REG;
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}
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return (ARM64Reg)(S0 + mr[r].reg);
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case ML_MEM:
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return INVALID_REG;
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default:
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ERROR_LOG_REPORT(JIT, "ARM64RegForFlush: MipsReg %d with invalid location %d", r, mr[r].loc);
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return INVALID_REG;
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}
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}
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void Arm64RegCacheFPU::FlushAll() {
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if (!pendingFlush) {
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// Nothing allocated. FPU regs are not nearly as common as GPR.
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return;
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}
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// Discard temps!
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for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; i++) {
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DiscardR(i);
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}
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int numArmRegs = 0;
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const ARM64Reg *order = GetMIPSAllocationOrder(numArmRegs);
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// Flush pairs first when possible. Note that STP's offset can't reach more than 256 bytes so
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// most VFPU registers cannot be flushed this way, unless we are willing to generate another offset pointer
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// (which we could actually do right here, point right in the middle of the VFPU stuff and would reach it all)... TODO
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for (int i = 0; i < 31; i++) {
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int mr1 = i;
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int mr2 = i + 1;
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ARM64Reg ar1 = ARM64RegForFlush(mr1);
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ARM64Reg ar2 = ARM64RegForFlush(mr2);
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if (ar1 != INVALID_REG && ar2 != INVALID_REG) {
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fp_->STP(32, INDEX_SIGNED, ar1, ar2, CTXREG, GetMipsRegOffset(mr1));
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DiscardR(mr1);
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DiscardR(mr2);
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}
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}
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// Then flush one by one.
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for (int i = 0; i < numArmRegs; i++) {
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int a = DecodeReg(order[i]);
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int m = ar[a].mipsReg;
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if (ar[a].isDirty) {
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if (m == -1) {
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ILOG("ARM reg %i is dirty but has no mipsreg", a);
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continue;
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}
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fp_->STR(32, INDEX_UNSIGNED, (ARM64Reg)(a + S0), CTXREG, GetMipsRegOffset(m));
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mr[m].loc = ML_MEM;
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mr[m].reg = (int)INVALID_REG;
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ar[a].mipsReg = -1;
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ar[a].isDirty = false;
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} else {
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if (m != -1) {
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mr[m].loc = ML_MEM;
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mr[m].reg = (int)INVALID_REG;
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}
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ar[a].mipsReg = -1;
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// already not dirty
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}
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}
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// Sanity check
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for (int i = 0; i < numARMFpuReg_; i++) {
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if (ar[i].mipsReg != -1) {
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ERROR_LOG(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);
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}
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}
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pendingFlush = false;
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}
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void Arm64RegCacheFPU::DiscardR(MIPSReg r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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// IMM is not allowed for FP (yet).
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ERROR_LOG(JIT, "Imm in FP register?");
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break;
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case ML_ARMREG:
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if (mr[r].reg == INVALID_REG) {
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ERROR_LOG(JIT, "DiscardR: MipsReg had bad ArmReg");
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} else {
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// Note that we DO NOT write it back here. That's the whole point of Discard.
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ar[mr[r].reg].isDirty = false;
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ar[mr[r].reg].mipsReg = -1;
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}
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break;
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case ML_MEM:
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// Already there, nothing to do.
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break;
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default:
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//BAD
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break;
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}
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mr[r].loc = ML_MEM;
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mr[r].reg = (int)INVALID_REG;
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mr[r].tempLock = false;
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mr[r].spillLock = false;
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}
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bool Arm64RegCacheFPU::IsTempX(ARM64Reg r) const {
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return ar[r - S0].mipsReg >= TEMP0;
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}
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int Arm64RegCacheFPU::GetTempR() {
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if (jo_->useASIMDVFPU) {
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ERROR_LOG(JIT, "VFP temps not allowed in NEON mode");
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return 0;
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}
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pendingFlush = true;
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for (int r = TEMP0; r < TEMP0 + NUM_TEMPS; ++r) {
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if (mr[r].loc == ML_MEM && !mr[r].tempLock) {
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mr[r].tempLock = true;
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return r;
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}
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|
}
|
|
|
|
ERROR_LOG(CPU, "Out of temp regs! Might need to DiscardR() some");
|
|
_assert_msg_(JIT, 0, "Regcache ran out of temp regs, might need to DiscardR() some.");
|
|
return -1;
|
|
}
|
|
|
|
int Arm64RegCacheFPU::GetMipsRegOffset(MIPSReg r) {
|
|
// These are offsets within the MIPSState structure. First there are the GPRS, then FPRS, then the "VFPURs", then the VFPU ctrls.
|
|
if (r < 0 || r > 32 + 128 + NUM_TEMPS) {
|
|
ERROR_LOG(JIT, "bad mips register %i, out of range", r);
|
|
return 0; // or what?
|
|
}
|
|
|
|
if (r < 32 || r >= 32 + 128) {
|
|
return (32 + r) << 2;
|
|
} else {
|
|
// r is between 32 and 128 + 32
|
|
return (32 + 32 + voffset[r - 32]) << 2;
|
|
}
|
|
}
|
|
|
|
void Arm64RegCacheFPU::SpillLock(MIPSReg r1, MIPSReg r2, MIPSReg r3, MIPSReg r4) {
|
|
mr[r1].spillLock = true;
|
|
if (r2 != -1) mr[r2].spillLock = true;
|
|
if (r3 != -1) mr[r3].spillLock = true;
|
|
if (r4 != -1) mr[r4].spillLock = true;
|
|
}
|
|
|
|
// This is actually pretty slow with all the 160 regs...
|
|
void Arm64RegCacheFPU::ReleaseSpillLocksAndDiscardTemps() {
|
|
for (int i = 0; i < NUM_MIPSFPUREG; i++) {
|
|
mr[i].spillLock = false;
|
|
}
|
|
for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; ++i) {
|
|
DiscardR(i);
|
|
}
|
|
}
|
|
|
|
ARM64Reg Arm64RegCacheFPU::R(int mipsReg) {
|
|
if (mr[mipsReg].loc == ML_ARMREG) {
|
|
return (ARM64Reg)(mr[mipsReg].reg + S0);
|
|
} else {
|
|
if (mipsReg < 32) {
|
|
ERROR_LOG(JIT, "FReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
|
|
} else if (mipsReg < 32 + 128) {
|
|
ERROR_LOG(JIT, "VReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
|
|
} else {
|
|
ERROR_LOG(JIT, "Tempreg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 128 - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
|
|
}
|
|
return INVALID_REG; // BAAAD
|
|
}
|
|
}
|
|
|
|
#endif // PPSSPP_ARCH(ARM64)
|