ppsspp/Core/MIPS/x86
Unknown W. Brackets 286c153c6a Fix memchecks for halfwords and bytes.
Before it was doing the range on a 4 byte read, which would trip a
memcheck that wasn't actually being hit if the byte of halfword was
unaligned.
2013-07-06 13:15:48 -07:00
..
Asm.cpp JIT: Get rid of one memory access per dispatch, and get rid of blockcodepointers. 2013-04-27 01:32:03 +02:00
Asm.h More armjit work 2013-01-08 00:26:42 +01:00
CompALU.cpp Handle the immediate case of clz/clo. 2013-07-04 23:07:42 -07:00
CompBranch.cpp Log more info about branches in delay slots. 2013-06-30 13:19:27 -07:00
CompFPU.cpp Add some basics for memory checks to x86 jit. 2013-03-09 02:41:46 -08:00
CompLoadStore.cpp Fix memchecks for halfwords and bytes. 2013-07-06 13:15:48 -07:00
CompVFPU.cpp Implement vmone/vmzero/vmidt for the x86 jit. 2013-07-04 18:16:57 -07:00
Jit.cpp Improve perf when ignore illegal is off. 2013-07-06 13:04:19 -07:00
Jit.h Re-enable lwl/lwr/swl/swr on the x86 jit. 2013-07-06 01:21:52 -07:00
RegCache.cpp Re-enable lwl/lwr/swl/swr on the x86 jit. 2013-07-06 01:21:52 -07:00
RegCache.h Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00
RegCacheFPU.cpp Fix some warnings generated by clang. 2013-02-24 10:23:31 -08:00
RegCacheFPU.h Try to reuse temp regs for better caching. 2013-02-18 00:32:42 -08:00