mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-11-24 05:49:58 +00:00
362 lines
8.3 KiB
C++
362 lines
8.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/CPU.h"
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#include "Core/Reporting.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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#include <limits>
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#define V(i) (currentMIPS->v[i])
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#define VI(i) (currentMIPS->vi[i])
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void GetVectorRegs(u8 regs[4], VectorSize N, int vectorReg) {
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int mtx = (vectorReg >> 2) & 7;
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int col = vectorReg & 3;
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int row = 0;
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int length = 0;
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int transpose = (vectorReg>>5) & 1;
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switch (N) {
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case V_Single: transpose = 0; row=(vectorReg>>5)&3; length = 1; break;
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case V_Pair: row=(vectorReg>>5)&2; length = 2; break;
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case V_Triple: row=(vectorReg>>6)&1; length = 3; break;
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case V_Quad: row=(vectorReg>>5)&2; length = 4; break;
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}
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for (int i = 0; i < length; i++) {
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int index = mtx * 4;
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if (transpose)
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index += ((row+i)&3) + col*32;
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else
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index += col + ((row+i)&3)*32;
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regs[i] = index;
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}
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}
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void GetMatrixRegs(u8 regs[16], MatrixSize N, int matrixReg) {
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int mtx = (matrixReg >> 2) & 7;
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int col = matrixReg & 3;
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int row = 0;
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int side = 0;
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switch (N) {
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case M_2x2: row = (matrixReg>>5)&2; side = 2; break;
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case M_3x3: row = (matrixReg>>6)&1; side = 3; break;
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case M_4x4: row = (matrixReg>>5)&2; side = 4; break;
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}
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int transpose = (matrixReg>>5) & 1;
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for (int i = 0; i < side; i++) {
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for (int j = 0; j < side; j++) {
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int index = mtx * 4;
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if (transpose)
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index += ((row+i)&3) + ((col+j)&3)*32;
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else
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index += ((col+j)&3) + ((row+i)&3)*32;
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regs[j*4 + i] = index;
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}
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}
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}
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void ReadVector(float *rd, VectorSize size, int reg) {
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const int mtx = (reg >> 2) & 7;
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const int col = reg & 3;
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int row = 0;
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int length = 0;
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int transpose = (reg>>5) & 1;
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switch (size) {
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case V_Single: transpose = 0; row=(reg>>5)&3; length = 1; break;
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case V_Pair: row=(reg>>5)&2; length = 2; break;
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case V_Triple: row=(reg>>6)&1; length = 3; break;
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case V_Quad: row=(reg>>5)&2; length = 4; break;
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}
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u32 *rdu = (u32 *)rd;
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if (transpose) {
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const int base = mtx * 4 + col * 32;
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for (int i = 0; i < length; i++)
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rdu[i] = VI(base + ((row+i)&3));
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} else {
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const int base = mtx * 4 + col;
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for (int i = 0; i < length; i++)
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rdu[i] = VI(base + ((row+i)&3)*32);
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}
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}
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void WriteVector(const float *rd, VectorSize size, int reg) {
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const int mtx = (reg>>2)&7;
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const int col = reg & 3;
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int row = 0;
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int length = 0;
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int transpose = (reg>>5)&1;
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switch (size) {
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case V_Single: transpose = 0; row=(reg>>5)&3; length = 1; break;
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case V_Pair: row=(reg>>5)&2; length = 2; break;
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case V_Triple: row=(reg>>6)&1; length = 3; break;
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case V_Quad: row=(reg>>5)&2; length = 4; break;
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}
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u32 *rdu = (u32 *)rd;
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if (currentMIPS->VfpuWriteMask() == 0) {
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if (transpose) {
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const int base = mtx * 4 + col * 32;
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for (int i = 0; i < length; i++)
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VI(base + ((row+i)&3)) = rdu[i];
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} else {
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const int base = mtx * 4 + col;
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for (int i = 0; i < length; i++)
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VI(base + ((row+i)&3)*32) = rdu[i];
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}
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} else {
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for (int i = 0; i < length; i++) {
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if (!currentMIPS->VfpuWriteMask(i)) {
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int index = mtx * 4;
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if (transpose)
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index += ((row+i)&3) + col*32;
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else
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index += col + ((row+i)&3)*32;
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VI(index) = rdu[i];
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}
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}
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}
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}
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void ReadMatrix(float *rd, MatrixSize size, int reg) {
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int mtx = (reg >> 2) & 7;
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int col = reg & 3;
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int row = 0;
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int side = 0;
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switch (size) {
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case M_2x2: row = (reg>>5)&2; side = 2; break;
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case M_3x3: row = (reg>>6)&1; side = 3; break;
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case M_4x4: row = (reg>>5)&2; side = 4; break;
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}
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int transpose = (reg>>5) & 1;
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for (int i = 0; i < side; i++) {
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for (int j = 0; j < side; j++) {
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int index = mtx * 4;
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if (transpose)
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index += ((row+i)&3) + ((col+j)&3)*32;
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else
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index += ((col+j)&3) + ((row+i)&3)*32;
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rd[j*4 + i] = V(index);
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}
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}
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}
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void WriteMatrix(const float *rd, MatrixSize size, int reg) {
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int mtx = (reg>>2)&7;
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int col = reg&3;
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int row = 0;
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int side = 0;
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switch (size) {
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case M_2x2: row = (reg>>5)&2; side = 2; break;
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case M_3x3: row = (reg>>6)&1; side = 3; break;
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case M_4x4: row = (reg>>5)&2; side = 4; break;
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}
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int transpose = (reg>>5)&1;
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if (currentMIPS->VfpuWriteMask() != 0) {
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ERROR_LOG_REPORT(CPU, "Write mask used with vfpu matrix instruction.");
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}
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for (int i=0; i<side; i++) {
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for (int j=0; j<side; j++) {
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// Hm, I wonder if this should affect matrices at all.
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if (j != side -1 || !currentMIPS->VfpuWriteMask(i))
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{
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int index = mtx * 4;
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if (transpose)
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index += ((row+i)&3) + ((col+j)&3)*32;
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else
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index += ((col+j)&3) + ((row+i)&3)*32;
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V(index) = rd[j*4+i];
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}
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}
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}
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}
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int GetNumVectorElements(VectorSize sz)
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{
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switch (sz)
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{
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case V_Single: return 1;
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case V_Pair: return 2;
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case V_Triple: return 3;
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case V_Quad: return 4;
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default: return 0;
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}
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}
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VectorSize GetHalfVectorSize(VectorSize sz)
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{
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switch (sz)
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{
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case V_Pair: return V_Single;
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case V_Quad: return V_Pair;
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default:
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return V_Single;
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}
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}
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VectorSize GetVecSize(MIPSOpcode op)
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{
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int a = (op>>7)&1;
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int b = (op>>15)&1;
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a += (b<<1);
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switch (a)
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{
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case 0: return V_Single;
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case 1: return V_Pair;
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case 2: return V_Triple;
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case 3: return V_Quad;
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default: return V_Quad;
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}
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}
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MatrixSize GetMtxSize(MIPSOpcode op)
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{
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int a = (op>>7)&1;
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int b = (op>>15)&1;
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a += (b<<1);
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switch (a)
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{
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case 0: ERROR_LOG_REPORT(CPU, "Unexpected matrix size 1x1."); return M_2x2;
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case 1: return M_2x2;
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case 2: return M_3x3;
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case 3: return M_4x4;
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default: return M_4x4;
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}
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}
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int GetMatrixSide(MatrixSize sz)
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{
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switch (sz)
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{
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case M_2x2: return 2;
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case M_3x3: return 3;
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case M_4x4: return 4;
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default: return 0;
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}
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}
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const char *GetVectorNotation(int reg, VectorSize size)
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{
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static char hej[4][16];
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static int yo=0;yo++;yo&=3;
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int mtx = (reg>>2)&7;
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int col = reg&3;
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int row = 0;
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int transpose = (reg>>5)&1;
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char c;
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switch (size)
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{
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case V_Single: transpose=0; c='S'; row=(reg>>5)&3; break;
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case V_Pair: c='C'; row=(reg>>5)&2; break;
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case V_Triple: c='C'; row=(reg>>6)&1; break;
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case V_Quad: c='C'; row=(reg>>5)&2; break;
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}
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if (transpose && c == 'C') c='R';
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if (transpose)
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sprintf(hej[yo],"%c%i%i%i",c,mtx,row,col);
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else
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sprintf(hej[yo],"%c%i%i%i",c,mtx,col,row);
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return hej[yo];
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}
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const char *GetMatrixNotation(int reg, MatrixSize size)
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{
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static char hej[4][16];
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static int yo=0;yo++;yo&=3;
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int mtx = (reg>>2)&7;
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int col = reg&3;
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int row = 0;
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int transpose = (reg>>5)&1;
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char c;
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switch (size)
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{
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case M_2x2: c='M'; row=(reg>>5)&2; break;
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case M_3x3: c='M'; row=(reg>>6)&1; break;
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case M_4x4: c='M'; row=(reg>>5)&2; break;
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}
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if (transpose && c=='M') c='E';
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sprintf(hej[yo],"%c%i%i%i",c,mtx,col,row);
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return hej[yo];
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}
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float Float16ToFloat32(unsigned short l)
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{
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union float2int {
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unsigned int i;
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float f;
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} float2int;
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unsigned short float16 = l;
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unsigned int sign = (float16 >> VFPU_SH_FLOAT16_SIGN) & VFPU_MASK_FLOAT16_SIGN;
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int exponent = (float16 >> VFPU_SH_FLOAT16_EXP) & VFPU_MASK_FLOAT16_EXP;
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unsigned int fraction = float16 & VFPU_MASK_FLOAT16_FRAC;
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float signf = (sign == 1) ? -1.0f : 1.0f;
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float f;
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if (exponent == VFPU_FLOAT16_EXP_MAX)
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{
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if (fraction == 0)
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f = std::numeric_limits<float>::infinity(); //(*info->fprintf_func) (info->stream, "%cInf", signchar);
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else
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f = std::numeric_limits<float>::quiet_NaN(); //(*info->fprintf_func) (info->stream, "%cNaN", signchar);
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}
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else if (exponent == 0 && fraction == 0)
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{
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f = 0.0f * signf;
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}
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else
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{
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if (exponent == 0)
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{
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do
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{
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fraction <<= 1;
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exponent--;
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}
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while (!(fraction & (VFPU_MASK_FLOAT16_FRAC + 1)));
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fraction &= VFPU_MASK_FLOAT16_FRAC;
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}
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/* Convert to 32-bit single-precision IEEE754. */
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float2int.i = sign << 31;
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float2int.i |= (exponent + 112) << 23;
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float2int.i |= fraction << 13;
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f=float2int.f;
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}
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return f;
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}
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