mirror of
https://github.com/hrydgard/ppsspp.git
synced 2024-10-07 10:53:31 +00:00
285 lines
9.8 KiB
C++
285 lines
9.8 KiB
C++
// Copyright (c) 2014- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include <functional>
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#include <stdint.h>
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#include "Common/CodeBlock.h"
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#include "Common/CommonTypes.h"
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namespace MIPSGen {
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enum MIPSReg {
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R_ZERO = 0,
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R_AT,
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V0, V1,
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A0 = 4, A1 = 5, A2 = 6, A3 = 7, A4 = 8, A5 = 9, A6 = 10, A7 = 11,
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// Alternate names depending on ABI.
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T0 = 8, T1 = 9, T2 = 10, T3 = 11,
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T4, T5, T6, T7,
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S0, S1, S2, S3, S4, S5, S6, S7,
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T8, T9,
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K0, K1,
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R_GP, R_SP, R_FP,
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R_RA,
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F_BASE = 32,
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F0 = 32, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,
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INVALID_REG = 0xFFFFFFFF
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};
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enum {
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// All 32 except: ZERO, K0/K1 (kernel), RA. The rest are only convention.
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NUMGPRs = 32 - 1 - 2 - 1,
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NUMFPRs = 32,
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};
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enum FixupBranchType {
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// 16-bit immediate jump/branch (to pc + (simm16 + 1 ops).)
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BRANCH_16,
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// 26-bit immediate jump/branch (to pc's 4 high bits + imm * 4.)
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BRANCH_26,
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};
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// Beware of delay slots.
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struct FixupBranch {
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u8 *ptr;
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FixupBranchType type;
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};
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class MIPSEmitter {
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public:
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MIPSEmitter() : code_(0), lastCacheFlushEnd_(0) {
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}
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MIPSEmitter(u8 *code_ptr) : code_(code_ptr), lastCacheFlushEnd_(code_ptr) {
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SetCodePointer(code_ptr, code_ptr);
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}
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virtual ~MIPSEmitter() {
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}
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void SetCodePointer(const u8 *ptr, u8 *writePtr);
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const u8* GetCodePointer() const;
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void ReserveCodeSpace(u32 bytes);
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr() const;
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u8 *GetWritableCodePtr();
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void FlushIcache();
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void FlushIcacheSection(u8 *start, u8 *end);
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// 20 bits valid in code.
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void BREAK(u32 code);
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void NOP() {
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SLL(R_ZERO, R_ZERO, 0);
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}
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// Note for all branches and jumps:
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// MIPS has DELAY SLOTS. This emitter makes it so if you forget that, you'll be safe.
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// If you want to run something inside a delay slot, emit the instruction inside a closure.
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//
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// Example: Translates to:
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// J(&myFunc); J(&myFunc);
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// ADDU(V0, V0, V1); NOP();
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// ADDU(V0, V0, V1);
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//
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// J(&myFunc, [&] { J(&myFunc);
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// ADDU(V0, V0, V1); ADDU(V0, V0, V1);
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// });
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//
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// This applies to all J*() and B*() functions (except BREAK(), which is not a branch func.)
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FixupBranch J(std::function<void ()> delaySlot = nullptr);
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void J(const void *func, std::function<void ()> delaySlot = nullptr);
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FixupBranch JAL(std::function<void ()> delaySlot = nullptr);
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void JAL(const void *func, std::function<void ()> delaySlot = nullptr);
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void JR(MIPSReg rs, std::function<void ()> delaySlot = nullptr);
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void JRRA(std::function<void ()> delaySlot = nullptr) {
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JR(R_RA, delaySlot);
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}
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void JALR(MIPSReg rd, MIPSReg rs, std::function<void ()> delaySlot = nullptr);
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void JALR(MIPSReg rs, std::function<void ()> delaySlot = nullptr) {
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JALR(R_RA, rs, delaySlot);
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}
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inline FixupBranch B(std::function<void ()> delaySlot = nullptr) {
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return BEQ(R_ZERO, R_ZERO, delaySlot);
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}
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inline void B(const void *func, std::function<void ()> delaySlot = nullptr) {
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return BEQ(R_ZERO, R_ZERO, func, delaySlot);
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}
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FixupBranch BLTZ(MIPSReg rs, std::function<void ()> delaySlot = nullptr);
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void BLTZ(MIPSReg rs, const void *func, std::function<void ()> delaySlot = nullptr);
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FixupBranch BEQ(MIPSReg rs, MIPSReg rt, std::function<void ()> delaySlot = nullptr);
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void BEQ(MIPSReg rs, MIPSReg rt, const void *func, std::function<void ()> delaySlot = nullptr);
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FixupBranch BNE(MIPSReg rs, MIPSReg rt, std::function<void ()> delaySlot = nullptr);
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void BNE(MIPSReg rs, MIPSReg rt, const void *func, std::function<void ()> delaySlot = nullptr);
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inline FixupBranch BEQZ(MIPSReg rs, std::function<void ()> delaySlot = nullptr) {
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return BEQ(rs, R_ZERO, delaySlot);
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}
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inline void BEQZ(MIPSReg rs, const void *func, std::function<void ()> delaySlot = nullptr) {
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return BEQ(rs, R_ZERO, func, delaySlot);
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}
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inline FixupBranch BNEZ(MIPSReg rs, std::function<void ()> delaySlot = nullptr) {
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return BNE(rs, R_ZERO, delaySlot);
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}
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inline void BNEZ(MIPSReg rs, const void *func, std::function<void ()> delaySlot = nullptr) {
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return BNE(rs, R_ZERO, func, delaySlot);
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}
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FixupBranch BLEZ(MIPSReg rs, std::function<void ()> delaySlot = nullptr);
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void BLEZ(MIPSReg rs, const void *func, std::function<void ()> delaySlot = nullptr);
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FixupBranch BGTZ(MIPSReg rs, std::function<void ()> delaySlot = nullptr);
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void BGTZ(MIPSReg rs, const void *func, std::function<void ()> delaySlot = nullptr);
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void SetJumpTarget(const FixupBranch &branch);
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bool BInRange(const void *func);
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bool JInRange(const void *func);
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// R_AT is the stereotypical scratch reg, but it is not likely to be used.
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void QuickCallFunction(MIPSReg scratchreg, const void *func);
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template <typename T> void QuickCallFunction(MIPSReg scratchreg, T func) {
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QuickCallFunction(scratchreg, (const void *)func);
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}
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void LB(MIPSReg dest, MIPSReg base, s16 offset);
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void LH(MIPSReg dest, MIPSReg base, s16 offset);
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void LW(MIPSReg dest, MIPSReg base, s16 offset);
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void SB(MIPSReg value, MIPSReg base, s16 offset);
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void SH(MIPSReg dest, MIPSReg base, s16 offset);
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void SW(MIPSReg value, MIPSReg base, s16 offset);
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// These exist for the sole purpose of making compilation fail if you try to load/store from R+R.
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void LB(MIPSReg dest, MIPSReg base, MIPSReg invalid);
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void LH(MIPSReg dest, MIPSReg base, MIPSReg invalid);
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void LW(MIPSReg dest, MIPSReg base, MIPSReg invalid);
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void SB(MIPSReg value, MIPSReg base, MIPSReg invalid);
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void SH(MIPSReg dest, MIPSReg base, MIPSReg invalid);
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void SW(MIPSReg value, MIPSReg base, MIPSReg invalid);
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void SLL(MIPSReg rd, MIPSReg rt, u8 sa);
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void SRL(MIPSReg rd, MIPSReg rt, u8 sa);
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void SRA(MIPSReg rd, MIPSReg rt, u8 sa);
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void SLLV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
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void SRLV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
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void SRAV(MIPSReg rd, MIPSReg rt, MIPSReg rs);
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void SLT(MIPSReg rd, MIPSReg rt, MIPSReg rs);
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void SLTU(MIPSReg rd, MIPSReg rt, MIPSReg rs);
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void SLTI(MIPSReg rd, MIPSReg rt, s16 imm);
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// Note: very importantly, *sign* extends imm before an unsigned compare.
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void SLTIU(MIPSReg rt, MIPSReg rs, s16 imm);
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// ADD/SUB/ADDI intentionally omitted. They are just versions that trap.
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void ADDU(MIPSReg rd, MIPSReg rs, MIPSReg rt);
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void SUBU(MIPSReg rd, MIPSReg rs, MIPSReg rt);
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void ADDIU(MIPSReg rt, MIPSReg rs, s16 imm);
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void SUBIU(MIPSReg rt, MIPSReg rs, s16 imm) {
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ADDIU(rt, rs, -imm);
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}
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void AND(MIPSReg rd, MIPSReg rs, MIPSReg rt);
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void OR(MIPSReg rd, MIPSReg rs, MIPSReg rt);
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void XOR(MIPSReg rd, MIPSReg rs, MIPSReg rt);
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void ANDI(MIPSReg rt, MIPSReg rs, s16 imm);
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void ORI(MIPSReg rt, MIPSReg rs, s16 imm);
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void XORI(MIPSReg rt, MIPSReg rs, s16 imm);
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// Clears the lower bits. On MIPS64, the result is sign extended.
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void LUI(MIPSReg rt, s16 imm);
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void INS(MIPSReg rt, MIPSReg rs, s8 pos, s8 size);
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void EXT(MIPSReg rt, MIPSReg rs, s8 pos, s8 size);
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// MIPS64 only. Transparently uses DSLL32 to shift 32-63 bits.
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void DSLL(MIPSReg rd, MIPSReg rt, u8 sa);
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void MOVI2R(MIPSReg reg, u64 val);
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void MOVI2R(MIPSReg reg, s64 val) {
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MOVI2R(reg, (u64)val);
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}
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void MOVI2R(MIPSReg reg, u32 val);
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void MOVI2R(MIPSReg reg, s32 val) {
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MOVI2R(reg, (u32)val);
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}
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template <class T> void MOVP2R(MIPSReg reg, T *val) {
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if (sizeof(uintptr_t) > sizeof(u32)) {
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MOVI2R(reg, (u64)(intptr_t)(const void *)val);
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} else {
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MOVI2R(reg, (u32)(intptr_t)(const void *)val);
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}
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}
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protected:
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inline void Write32(u32 value) {
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*code32_++ = value;
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}
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// Less parenthesis.
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inline void Write32Fields(u8 pos1, u32 v1) {
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*code32_++ = (v1 << pos1);
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}
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inline void Write32Fields(u8 pos1, u32 v1, u8 pos2, u32 v2) {
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*code32_++ = (v1 << pos1) | (v2 << pos2);
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}
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inline void Write32Fields(u8 pos1, u32 v1, u8 pos2, u32 v2, u8 pos3, u32 v3) {
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*code32_++ = (v1 << pos1) | (v2 << pos2) | (v3 << pos3);
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}
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inline void Write32Fields(u8 pos1, u32 v1, u8 pos2, u32 v2, u8 pos3, u32 v3, u8 pos4, u32 v4) {
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*code32_++ = (v1 << pos1) | (v2 << pos2) | (v3 << pos3) | (v4 << pos4);
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}
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inline void Write32Fields(u8 pos1, u32 v1, u8 pos2, u32 v2, u8 pos3, u32 v3, u8 pos4, u32 v4, u8 pos5, u32 v5) {
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*code32_++ = (v1 << pos1) | (v2 << pos2) | (v3 << pos3) | (v4 << pos5) | (v5 << pos5);
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}
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inline void Write32Fields(u8 pos1, u32 v1, u8 pos2, u32 v2, u8 pos3, u32 v3, u8 pos4, u32 v4, u8 pos5, u32 v5, u8 pos6, u32 v6) {
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*code32_++ = (v1 << pos1) | (v2 << pos2) | (v3 << pos3) | (v4 << pos5) | (v5 << pos5) | (v6 << pos6);
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}
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static void SetJumpTarget(const FixupBranch &branch, const void *dst);
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static bool BInRange(const void *src, const void *dst);
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static bool JInRange(const void *src, const void *dst);
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FixupBranch MakeFixupBranch(FixupBranchType type);
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void ApplyDelaySlot(std::function<void ()> delaySlot);
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private:
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union {
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u8 *code_;
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u32 *code32_;
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};
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u8 *lastCacheFlushEnd_;
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};
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// Everything that needs to generate machine code should inherit from this.
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// You get memory management for free, plus, you can use all the LUI etc functions without
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// having to prefix them with gen-> or something similar.
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class MIPSCodeBlock : public CodeBlock<MIPSEmitter> {
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public:
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void PoisonMemory(int offset) override;
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protected:
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u8 *region;
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size_t region_size;
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};
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};
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