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33 lines
2.3 KiB
Markdown
33 lines
2.3 KiB
Markdown
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# FEXCore IR
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---
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The IR for the FEXCore is an SSA based IR that is generated from the incoming x86-64 assembly.
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SSA is quite nice to work with when translating the x86-64 code to the IR, when optimizing that code with custom optimization passes, and also passing that IR to our CPU backends.
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## Emulation IR considerations
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* We have explicitly sized IR variables
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* Supports traditional element sizes of 1,2,4,8 bytes and some 16byte ops
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* Supports arbitrary number of vector elements
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* The op determines if something is float or integer based.
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* Clear separation of scalar IR ops and vector IR ops
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* ex, MUL versus VMUL
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* We have explicit Load/Store context IR ops
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* This allows us to have a clear separation between guest memory and tracked x86-64 state
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* We have an explicit CPUID IR op
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* This allows us to return fairly complex data (4 registers of data) and also having an easier optimization for constant CPUID functions
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* So if we const-prop the CPUID function then it'll just const-prop further along
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* We have an explicit syscall op
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* The syscall op is fairly complex as well, same with CPUID that if the syscall function is const-prop then we can directly call the syscall handler
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* Can save overhead by removing call overheads
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* The IR supports branching from one block to another
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* Has a conditional branch instruction that either branches to the target branch or falls through to the next block
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* Has an unconditional branch to explicitly jump to a block instead of falling through
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* **There is a desire to follow LLVM semantics around block limitations but it isn't currently strictly enforced**
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* Supports a debug ```Print``` Op for printing out values for debug viewing
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* Supports explicit Load/Store memory IR ops
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* This is for accessing guest memory and will do the memory offset translation in to the VM's memory space
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* This is done by just adding the VM memory base to the 64bit address passed in
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* This is done in a manner that the application **can** escape from the VM and isn't meant to be safe
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* There is an option for JITs to validate the memory region prior to accessing for ensuring correctness
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* IR is generated from a JSON file, fairly straightforward to extend.
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* Read the python generation file to determine the extent of what it can do
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