diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 11e71668b..8d30ad70e 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -15,10 +15,10 @@ "Comment": "0x00", "ExpectedArm64ASM": [ "ldaddalb w5, w20, [x4]", - "add w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #24", - "cmn w0, w5, lsl #24" + "cmn w0, w5, lsl #24", + "add w26, w20, w5" ] }, "lock add word [rax], cx": { @@ -26,20 +26,19 @@ "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddalh w5, w20, [x4]", - "add w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #16", - "cmn w0, w5, lsl #16" + "cmn w0, w5, lsl #16", + "add w26, w20, w5" ] }, "lock add dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal w5, w20, [x4]", - "add w26, w20, w5", "eor w27, w20, w5", - "cmn w20, w5" + "adds w26, w20, w5" ] }, "lock or byte [rax], cl": { @@ -251,10 +250,10 @@ "ExpectedArm64ASM": [ "neg w1, w5", "ldaddalb w1, w20, [x4]", - "sub w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #24", "cmp w0, w5, lsl #24", + "sub w26, w20, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -266,24 +265,23 @@ "ExpectedArm64ASM": [ "neg w1, w5", "ldaddalh w1, w20, [x4]", - "sub w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #16", "cmp w0, w5, lsl #16", + "sub w26, w20, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub dword [rax], ecx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x29", "ExpectedArm64ASM": [ "neg w1, w5", "ldaddal w1, w20, [x4]", - "sub w26, w20, w5", "eor w27, w20, w5", - "cmp w20, w5", + "subs w26, w20, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -317,13 +315,12 @@ ] }, "lock add qword [rax], rcx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", - "add x26, x20, x5", "eor w27, w20, w5", - "cmn x20, x5" + "adds x26, x20, x5" ] }, "xchg byte [rax], cl": { @@ -367,10 +364,10 @@ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w21, w20" ] }, "xadd word [rax], bx": { @@ -380,32 +377,30 @@ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w21, w20" ] }, "xadd dword [rax], ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w26, w7, w20", "eor w27, w7, w20", - "cmn w7, w20" + "adds w26, w7, w20" ] }, "xadd qword [rax], rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x26, x7, x20", "eor w27, w7, w20", - "cmn x7, x20" + "adds x26, x7, x20" ] }, "lock add byte [rax], 1": { @@ -414,9 +409,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "lsl w0, w27, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w27, #0x1 (1)" ] }, "lock add byte [rax], 0xFF": { @@ -425,10 +420,10 @@ "ExpectedArm64ASM": [ "mov w20, #0xff", "ldaddalb w20, w21, [x4]", - "add w26, w21, #0xff (255)", "eor w27, w21, #0xff", "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w21, #0xff (255)" ] }, "lock add word [rax], 0x100": { @@ -437,9 +432,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddalh w20, w27, [x4]", - "add w26, w27, #0x100 (256)", "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w27, #0x100 (256)" ] }, "lock add word [rax], 0xFFFF": { @@ -448,51 +443,47 @@ "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldaddalh w20, w21, [x4]", - "add w26, w21, w20", "eor w27, w21, #0xffff", "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w21, w20" ] }, "lock add dword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal w20, w27, [x4]", - "add w26, w27, #0x100 (256)", - "cmn w27, #0x100 (256)" + "adds w26, w27, #0x100 (256)" ] }, "lock add dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w21, [x4]", - "add w26, w21, w20", "eor w27, w21, w20", - "cmn w21, w20" + "adds w26, w21, w20" ] }, "lock add qword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal x20, x27, [x4]", - "add x26, x27, #0x100 (256)", - "cmn x27, #0x100 (256)" + "adds x26, x27, #0x100 (256)" ] }, "lock add qword [rax], -2147483647": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldaddal x20, x27, [x4]", - "add x26, x27, x20", - "cmn x27, x20" + "adds x26, x27, x20" ] }, "lock add word [rax], 1": { @@ -501,29 +492,27 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w27, #0x1 (1)" ] }, "lock add dword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "add w26, w27, #0x1 (1)", - "cmn w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)" ] }, "lock add qword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "add x26, x27, #0x1 (1)", - "cmn x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)" ] }, "lock or byte [rax], 1": { @@ -1205,9 +1194,9 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalb w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1220,10 +1209,10 @@ "mov w20, #0xff", "neg w1, w20", "ldaddalb w1, w21, [x4]", - "sub w26, w21, #0xff (255)", "eor w27, w21, #0xff", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", + "sub w26, w21, #0xff (255)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1236,9 +1225,9 @@ "mov w20, #0x100", "neg w1, w20", "ldaddalh w1, w27, [x4]", - "sub w26, w27, #0x100 (256)", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1251,67 +1240,63 @@ "mov w20, #0xffff", "neg w1, w20", "ldaddalh w1, w21, [x4]", - "sub w26, w21, w20", "eor w27, w21, #0xffff", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", + "sub w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub dword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", "ldaddal w1, w27, [x4]", - "sub w26, w27, #0x100 (256)", - "cmp w27, #0x100 (256)", + "subs w26, w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "neg w1, w20", "ldaddal w1, w21, [x4]", - "sub w26, w21, w20", "eor w27, w21, w20", - "cmp w21, w20", + "subs w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub qword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, #0x100 (256)", - "cmp x27, #0x100 (256)", + "subs x26, x27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub qword [rax], -2147483647": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, x20", - "cmp x27, x20", + "subs x26, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1324,37 +1309,35 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalh w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub dword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", "ldaddal w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub qword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, #0x1 (1)", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1477,10 +1460,10 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalb w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", "msr nzcv, x20" @@ -1527,8 +1510,8 @@ "stlxrb w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "neg w26, w27", "cmp wzr, w27, lsl #24", + "neg w26, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1543,15 +1526,15 @@ "stlxrh w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "neg w26, w27", "cmp wzr, w27, lsl #16", + "neg w26, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock neg dword [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr w1, [x4]", @@ -1559,15 +1542,14 @@ "stlxr w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "neg w26, w27", - "cmp wzr, w27", + "negs w26, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock neg qword [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr x1, [x4]", @@ -1575,8 +1557,7 @@ "stlxr w3, x2, [x4]", "cbnz x3, #-0xc", "mov x27, x1", - "neg x26, x27", - "cmp xzr, x27", + "negs x26, x27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1589,25 +1570,24 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalh w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, "lock dec dword [rax]": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", "ldaddal w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "cset w20, hs", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -1616,15 +1596,14 @@ ] }, "lock dec qword [rax]": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, #0x1 (1)", "cset w20, hs", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -1638,10 +1617,10 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", + "add w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", "msr nzcv, x20" @@ -1653,24 +1632,23 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", + "add w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, "lock inc dword [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "cset w20, hs", - "cmn w27, #0x1 (1)", + "adds w26, w27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -1679,14 +1657,13 @@ ] }, "lock inc qword [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "add x26, x27, #0x1 (1)", "cset w20, hs", - "cmn x27, #0x1 (1)", + "adds x26, x27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 71a0a7aa4..d3582de97 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -16,10 +16,10 @@ "Comment": "0x00", "ExpectedArm64ASM": [ "ldaddalb w5, w20, [x4]", - "add w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #24", - "cmn w0, w5, lsl #24" + "cmn w0, w5, lsl #24", + "add w26, w20, w5" ] }, "lock add word [rax], cx": { @@ -27,20 +27,19 @@ "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddalh w5, w20, [x4]", - "add w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #16", - "cmn w0, w5, lsl #16" + "cmn w0, w5, lsl #16", + "add w26, w20, w5" ] }, "lock add dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal w5, w20, [x4]", - "add w26, w20, w5", "eor w27, w20, w5", - "cmn w20, w5" + "adds w26, w20, w5" ] }, "lock or byte [rax], cl": { @@ -244,10 +243,10 @@ "ExpectedArm64ASM": [ "neg w1, w5", "ldaddalb w1, w20, [x4]", - "sub w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #24", "cmp w0, w5, lsl #24", + "sub w26, w20, w5", "cfinv" ] }, @@ -257,22 +256,21 @@ "ExpectedArm64ASM": [ "neg w1, w5", "ldaddalh w1, w20, [x4]", - "sub w26, w20, w5", "eor w27, w20, w5", "lsl w0, w20, #16", "cmp w0, w5, lsl #16", + "sub w26, w20, w5", "cfinv" ] }, "lock sub dword [rax], ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x29", "ExpectedArm64ASM": [ "neg w1, w5", "ldaddal w1, w20, [x4]", - "sub w26, w20, w5", "eor w27, w20, w5", - "cmp w20, w5", + "subs w26, w20, w5", "cfinv" ] }, @@ -304,13 +302,12 @@ ] }, "lock add qword [rax], rcx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", - "add x26, x20, x5", "eor w27, w20, w5", - "cmn x20, x5" + "adds x26, x20, x5" ] }, "xadd byte [rax], bl": { @@ -320,10 +317,10 @@ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w21, w20" ] }, "xadd word [rax], bx": { @@ -333,32 +330,30 @@ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w21, w20" ] }, "xadd dword [rax], ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w26, w7, w20", "eor w27, w7, w20", - "cmn w7, w20" + "adds w26, w7, w20" ] }, "xadd qword [rax], rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x26, x7, x20", "eor w27, w7, w20", - "cmn x7, x20" + "adds x26, x7, x20" ] }, "lock add byte [rax], 1": { @@ -367,9 +362,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "lsl w0, w27, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w27, #0x1 (1)" ] }, "lock add byte [rax], 0xFF": { @@ -378,10 +373,10 @@ "ExpectedArm64ASM": [ "mov w20, #0xff", "ldaddalb w20, w21, [x4]", - "add w26, w21, #0xff (255)", "eor w27, w21, #0xff", "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w21, #0xff (255)" ] }, "lock add word [rax], 0x100": { @@ -390,9 +385,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddalh w20, w27, [x4]", - "add w26, w27, #0x100 (256)", "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w27, #0x100 (256)" ] }, "lock add word [rax], 0xFFFF": { @@ -401,51 +396,47 @@ "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldaddalh w20, w21, [x4]", - "add w26, w21, w20", "eor w27, w21, #0xffff", "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w21, w20" ] }, "lock add dword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal w20, w27, [x4]", - "add w26, w27, #0x100 (256)", - "cmn w27, #0x100 (256)" + "adds w26, w27, #0x100 (256)" ] }, "lock add dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w21, [x4]", - "add w26, w21, w20", "eor w27, w21, w20", - "cmn w21, w20" + "adds w26, w21, w20" ] }, "lock add qword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal x20, x27, [x4]", - "add x26, x27, #0x100 (256)", - "cmn x27, #0x100 (256)" + "adds x26, x27, #0x100 (256)" ] }, "lock add qword [rax], -2147483647": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldaddal x20, x27, [x4]", - "add x26, x27, x20", - "cmn x27, x20" + "adds x26, x27, x20" ] }, "lock add word [rax], 1": { @@ -454,29 +445,27 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w27, #0x1 (1)" ] }, "lock add dword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "add w26, w27, #0x1 (1)", - "cmn w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)" ] }, "lock add qword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "add x26, x27, #0x1 (1)", - "cmn x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)" ] }, "lock or byte [rax], 1": { @@ -1124,9 +1113,9 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalb w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "cfinv" ] }, @@ -1137,10 +1126,10 @@ "mov w20, #0xff", "neg w1, w20", "ldaddalb w1, w21, [x4]", - "sub w26, w21, #0xff (255)", "eor w27, w21, #0xff", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", + "sub w26, w21, #0xff (255)", "cfinv" ] }, @@ -1151,9 +1140,9 @@ "mov w20, #0x100", "neg w1, w20", "ldaddalh w1, w27, [x4]", - "sub w26, w27, #0x100 (256)", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x100 (256)", "cfinv" ] }, @@ -1164,59 +1153,55 @@ "mov w20, #0xffff", "neg w1, w20", "ldaddalh w1, w21, [x4]", - "sub w26, w21, w20", "eor w27, w21, #0xffff", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", + "sub w26, w21, w20", "cfinv" ] }, "lock sub dword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", "ldaddal w1, w27, [x4]", - "sub w26, w27, #0x100 (256)", - "cmp w27, #0x100 (256)", + "subs w26, w27, #0x100 (256)", "cfinv" ] }, "lock sub dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "neg w1, w20", "ldaddal w1, w21, [x4]", - "sub w26, w21, w20", "eor w27, w21, w20", - "cmp w21, w20", + "subs w26, w21, w20", "cfinv" ] }, "lock sub qword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, #0x100 (256)", - "cmp x27, #0x100 (256)", + "subs x26, x27, #0x100 (256)", "cfinv" ] }, "lock sub qword [rax], -2147483647": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, x20", - "cmp x27, x20", + "subs x26, x27, x20", "cfinv" ] }, @@ -1227,33 +1212,31 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalh w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "cfinv" ] }, "lock sub dword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", "ldaddal w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "cfinv" ] }, "lock sub qword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, #0x1 (1)", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "cfinv" ] }, @@ -1374,10 +1357,10 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalb w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "rmif x21, #63, #nzCv" ] }, @@ -1422,8 +1405,8 @@ "stlxrb w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "neg w26, w27", "cmp wzr, w27, lsl #24", + "neg w26, w27", "cfinv" ] }, @@ -1436,13 +1419,13 @@ "stlxrh w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "neg w26, w27", "cmp wzr, w27, lsl #16", + "neg w26, w27", "cfinv" ] }, "lock neg dword [rax]": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr w1, [x4]", @@ -1450,13 +1433,12 @@ "stlxr w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "neg w26, w27", - "cmp wzr, w27", + "negs w26, w27", "cfinv" ] }, "lock neg qword [rax]": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr x1, [x4]", @@ -1464,8 +1446,7 @@ "stlxr w3, x2, [x4]", "cbnz x3, #-0xc", "mov x27, x1", - "neg x26, x27", - "cmp xzr, x27", + "negs x26, x27", "cfinv" ] }, @@ -1476,36 +1457,34 @@ "mov w20, #0x1", "neg w1, w20", "ldaddalh w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "rmif x21, #63, #nzCv" ] }, "lock dec dword [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", "ldaddal w1, w27, [x4]", - "sub w26, w27, #0x1 (1)", "cset w20, hs", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "rmif x20, #63, #nzCv" ] }, "lock dec qword [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", "ldaddal x1, x27, [x4]", - "sub x26, x27, #0x1 (1)", "cset w20, hs", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "rmif x20, #63, #nzCv" ] }, @@ -1515,10 +1494,10 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", + "add w26, w27, #0x1 (1)", "rmif x21, #63, #nzCv" ] }, @@ -1528,34 +1507,32 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "cset w21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", + "add w26, w27, #0x1 (1)", "rmif x21, #63, #nzCv" ] }, "lock inc dword [rax]": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "add w26, w27, #0x1 (1)", "cset w20, hs", - "cmn w27, #0x1 (1)", + "adds w26, w27, #0x1 (1)", "rmif x20, #63, #nzCv" ] }, "lock inc qword [rax]": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "add x26, x27, #0x1 (1)", "cset w20, hs", - "cmn x27, #0x1 (1)", + "adds x26, x27, #0x1 (1)", "rmif x20, #63, #nzCv" ] } diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index d5e3892cf..6264628e3 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -11,15 +11,13 @@ }, "Instructions": { "Chained add": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "x86Insts": [ "add rax, rbx", "adc rcx, rcx" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, x7", - "cmn x20, x7", + "adds x4, x4, x7", "mov x20, x5", "cset w21, hs", "add x21, x20, x21", @@ -30,15 +28,13 @@ ] }, "Chained sub": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "x86Insts": [ "sub rax, rbx", "sbb rcx, rdx" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, x7", - "cmp x20, x7", + "subs x4, x4, x7", "cfinv", "cset w20, hs", "add x20, x6, x20", @@ -52,16 +48,14 @@ ] }, "Inverted add": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "x86Insts": [ "add rax, rbx", "adc rcx, rdx", "cmc" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, x7", - "cmn x20, x7", + "adds x4, x4, x7", "cset w20, hs", "add x20, x6, x20", "mov x21, x5", @@ -73,16 +67,14 @@ ] }, "Inverted sub": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "x86Insts": [ "sub rax, rbx", "sbb rcx, rcx", "cmc" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, x7", - "cmp x20, x7", + "subs x4, x4, x7", "cfinv", "mov x20, x5", "cset w21, hs", @@ -97,22 +89,18 @@ ] }, "INC consumed": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 6, "x86Insts": [ "add rax, rbx", "inc rax" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "add x21, x20, x7", - "mov x4, x21", - "add x4, x21, #0x1 (1)", - "cmn x20, x7", - "mov x27, x21", - "mov x26, x4", + "adds x4, x4, x7", "cset w20, hs", - "cmn x21, #0x1 (1)", - "rmif x20, #63, #nzCv" + "mov x27, x4", + "adds x26, x4, #0x1 (1)", + "rmif x20, #63, #nzCv", + "mov x4, x26" ] }, "INC dead": { @@ -129,23 +117,19 @@ ] }, "DEC consumed": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "x86Insts": [ "sub rax, rbx", "dec rax" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x21, x20, x7", - "mov x4, x21", - "sub x4, x21, #0x1 (1)", - "cmp x20, x7", + "subs x4, x4, x7", "cfinv", - "mov x27, x21", - "mov x26, x4", "cset w20, hs", - "cmp x21, #0x1 (1)", - "rmif x20, #63, #nzCv" + "mov x27, x4", + "subs x26, x4, #0x1 (1)", + "rmif x20, #63, #nzCv", + "mov x4, x26" ] }, "DEC dead": { @@ -205,7 +189,7 @@ "test cl, cl" ], "ExpectedArm64ASM": [ - "cmp x4, x7", + "subs x20, x4, x7", "cset x20, eq", "bfxil x5, x20, #0, #8", "mov x26, x5", @@ -213,16 +197,14 @@ ] }, "Partial NZCV select (add)": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "x86Insts": [ "add rax, rbx", "setz cl", "test cl, cl" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, x7", - "cmn x20, x7", + "adds x4, x4, x7", "cset x20, eq", "bfxil x5, x20, #0, #8", "mov x26, x5", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index b59bacf82..2d7527798 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -13,7 +13,7 @@ }, "Instructions": { "The Witcher 3": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "x86Insts": [ "mov eax, 0x1", "lock xadd qword [rcx], rax", @@ -29,16 +29,14 @@ "mov x6, x4", "and w6, w4, #0x1f", "add x6, x6, #0x1 (1)", - "lsl x20, x6, #6", - "mov x6, x20", - "add x6, x20, x5", - "eor w27, w20, w5", - "mov x26, x6", - "cmn x20, x5" + "lsl x6, x6, #6", + "eor w27, w6, w5", + "adds x26, x6, x5", + "mov x6, x26" ] }, "FMOD scalar loop": { - "ExpectedInstructionCount": 90, + "ExpectedInstructionCount": 88, "x86Insts": [ "mov esi, ecx", "mov rdx, rbp", @@ -80,8 +78,7 @@ "sub esi, 0x1" ], "ExpectedArm64ASM": [ - "mov w20, w5", - "mov x10, x20", + "mov w10, w5", "mov x6, x9", "mov x4, x7", "ldr s18, [x6]", @@ -89,91 +86,90 @@ "fmul s0, s18, s16", "mov v18.s[0], v0.s[0]", "add x6, x6, #0x20 (32)", - "sub x21, x4, #0x20 (32)", - "ldr s2, [x21]", + "sub x20, x4, #0x20 (32)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x20 (32)", - "str s18, [x21]", - "sub x21, x6, #0x1c (28)", - "ldr s18, [x21]", + "sub x20, x4, #0x20 (32)", + "str s18, [x20]", + "sub x20, x6, #0x1c (28)", + "ldr s18, [x20]", "fmul s0, s18, s17", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x1c (28)", - "ldr s2, [x21]", + "sub x20, x4, #0x1c (28)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x1c (28)", - "str s18, [x21]", - "sub x21, x6, #0x18 (24)", - "ldr s18, [x21]", + "sub x20, x4, #0x1c (28)", + "str s18, [x20]", + "sub x20, x6, #0x18 (24)", + "ldr s18, [x20]", "fmul s0, s18, s16", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x18 (24)", - "ldr s2, [x21]", + "sub x20, x4, #0x18 (24)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x18 (24)", - "str s18, [x21]", - "sub x21, x6, #0x14 (20)", - "ldr s18, [x21]", + "sub x20, x4, #0x18 (24)", + "str s18, [x20]", + "sub x20, x6, #0x14 (20)", + "ldr s18, [x20]", "fmul s0, s18, s17", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x14 (20)", - "ldr s2, [x21]", + "sub x20, x4, #0x14 (20)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x14 (20)", - "str s18, [x21]", - "sub x21, x6, #0x10 (16)", - "ldr s18, [x21]", + "sub x20, x4, #0x14 (20)", + "str s18, [x20]", + "sub x20, x6, #0x10 (16)", + "ldr s18, [x20]", "fmul s0, s18, s16", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x10 (16)", - "ldr s2, [x21]", + "sub x20, x4, #0x10 (16)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x10 (16)", - "str s18, [x21]", - "sub x21, x6, #0xc (12)", - "ldr s18, [x21]", + "sub x20, x4, #0x10 (16)", + "str s18, [x20]", + "sub x20, x6, #0xc (12)", + "ldr s18, [x20]", "fmul s0, s18, s17", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0xc (12)", - "ldr s2, [x21]", + "sub x20, x4, #0xc (12)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0xc (12)", - "str s18, [x21]", - "sub x21, x6, #0x8 (8)", - "ldr s18, [x21]", + "sub x20, x4, #0xc (12)", + "str s18, [x20]", + "sub x20, x6, #0x8 (8)", + "ldr s18, [x20]", "fmul s0, s18, s16", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x8 (8)", - "ldr s2, [x21]", + "sub x20, x4, #0x8 (8)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x8 (8)", - "str s18, [x21]", - "sub x21, x6, #0x4 (4)", - "ldr s18, [x21]", + "sub x20, x4, #0x8 (8)", + "str s18, [x20]", + "sub x20, x6, #0x4 (4)", + "ldr s18, [x20]", "fmul s0, s18, s17", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x4 (4)", - "ldr s2, [x21]", + "sub x20, x4, #0x4 (4)", + "ldr s2, [x20]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", - "sub x21, x4, #0x4 (4)", - "str s18, [x21]", - "sub w10, w20, #0x1 (1)", - "mov x27, x20", - "mov x26, x10", - "cmp w20, #0x1 (1)", - "cfinv" + "sub x20, x4, #0x4 (4)", + "str s18, [x20]", + "mov x27, x10", + "subs w26, w10, #0x1 (1)", + "cfinv", + "mov x10, x26" ] }, "Scalar vector add loop": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": [ "Saw this in bytemark" ], @@ -191,14 +187,13 @@ "add x20, x16, x4", "str q16, [x20]", "add x4, x4, #0x10 (16)", - "sub x26, x10, x4", "eor w27, w10, w4", - "cmp x10, x4", + "subs x26, x10, x4", "cfinv" ] }, "bytemark data xor loop": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "Saw this in bytemark" ], @@ -227,9 +222,8 @@ "eor x20, x20, x19", "add x21, x7, x6, lsl #3", "str x20, [x21]", - "sub x26, x11, x4", "eor w27, w11, w4", - "cmp x11, x4", + "subs x26, x11, x4", "cfinv" ] } diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 891beb90a..d981a7f09 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -12,7 +12,7 @@ }, "Instructions": { "Sonic Mania movie player": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": "Used to be hottest block in Sonic Mania", "x86Insts": [ "movzx edx, byte [esi+ecx]", @@ -41,14 +41,13 @@ "orr w20, w20, w6", "str w20, [x4]", "add w4, w4, #0x4 (4)", - "sub w26, w10, w7", "eor w27, w10, w7", - "cmp w10, w7", + "subs w26, w10, w7", "cfinv" ] }, "wine mscrt.dll memmove": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 20, "Comment": "Hot in Sonic Mania", "x86Insts": [ "movdqu xmm0, [esi]", @@ -82,9 +81,8 @@ "add w10, w10, #0x40 (64)", "add w11, w11, #0x40 (64)", "sub w5, w5, #0x40 (64)", - "sub w26, w5, #0x40 (64)", "mov w27, w5", - "cmp w5, #0x40 (64)", + "subs w26, w5, #0x40 (64)", "cfinv" ] } diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 4e8358d61..f1871c91a 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -13,7 +13,7 @@ }, "Instructions": { "FMOD scalar loop": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 72, "x86Insts": [ "mov esi, ecx", "mov rdx, rbp", @@ -55,80 +55,78 @@ "sub esi, 0x1" ], "ExpectedArm64ASM": [ - "mov w20, w5", - "mov x10, x20", + "mov w10, w5", "mov x6, x9", "mov x4, x7", "ldr s18, [x6]", "add x4, x4, #0x20 (32)", "fmul s18, s18, s16", "add x6, x6, #0x20 (32)", - "sub x21, x4, #0x20 (32)", - "ldr s2, [x21]", + "sub x20, x4, #0x20 (32)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x20 (32)", - "str s18, [x21]", - "sub x21, x6, #0x1c (28)", - "ldr s18, [x21]", + "sub x20, x4, #0x20 (32)", + "str s18, [x20]", + "sub x20, x6, #0x1c (28)", + "ldr s18, [x20]", "fmul s18, s18, s17", - "sub x21, x4, #0x1c (28)", - "ldr s2, [x21]", + "sub x20, x4, #0x1c (28)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x1c (28)", - "str s18, [x21]", - "sub x21, x6, #0x18 (24)", - "ldr s18, [x21]", + "sub x20, x4, #0x1c (28)", + "str s18, [x20]", + "sub x20, x6, #0x18 (24)", + "ldr s18, [x20]", "fmul s18, s18, s16", - "sub x21, x4, #0x18 (24)", - "ldr s2, [x21]", + "sub x20, x4, #0x18 (24)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x18 (24)", - "str s18, [x21]", - "sub x21, x6, #0x14 (20)", - "ldr s18, [x21]", + "sub x20, x4, #0x18 (24)", + "str s18, [x20]", + "sub x20, x6, #0x14 (20)", + "ldr s18, [x20]", "fmul s18, s18, s17", - "sub x21, x4, #0x14 (20)", - "ldr s2, [x21]", + "sub x20, x4, #0x14 (20)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x14 (20)", - "str s18, [x21]", - "sub x21, x6, #0x10 (16)", - "ldr s18, [x21]", + "sub x20, x4, #0x14 (20)", + "str s18, [x20]", + "sub x20, x6, #0x10 (16)", + "ldr s18, [x20]", "fmul s18, s18, s16", - "sub x21, x4, #0x10 (16)", - "ldr s2, [x21]", + "sub x20, x4, #0x10 (16)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x10 (16)", - "str s18, [x21]", - "sub x21, x6, #0xc (12)", - "ldr s18, [x21]", + "sub x20, x4, #0x10 (16)", + "str s18, [x20]", + "sub x20, x6, #0xc (12)", + "ldr s18, [x20]", "fmul s18, s18, s17", - "sub x21, x4, #0xc (12)", - "ldr s2, [x21]", + "sub x20, x4, #0xc (12)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0xc (12)", - "str s18, [x21]", - "sub x21, x6, #0x8 (8)", - "ldr s18, [x21]", + "sub x20, x4, #0xc (12)", + "str s18, [x20]", + "sub x20, x6, #0x8 (8)", + "ldr s18, [x20]", "fmul s18, s18, s16", - "sub x21, x4, #0x8 (8)", - "ldr s2, [x21]", + "sub x20, x4, #0x8 (8)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x8 (8)", - "str s18, [x21]", - "sub x21, x6, #0x4 (4)", - "ldr s18, [x21]", + "sub x20, x4, #0x8 (8)", + "str s18, [x20]", + "sub x20, x6, #0x4 (4)", + "ldr s18, [x20]", "fmul s18, s18, s17", - "sub x21, x4, #0x4 (4)", - "ldr s2, [x21]", + "sub x20, x4, #0x4 (4)", + "ldr s2, [x20]", "fadd s18, s18, s2", - "sub x21, x4, #0x4 (4)", - "str s18, [x21]", - "sub w10, w20, #0x1 (1)", - "mov x27, x20", - "mov x26, x10", - "cmp w20, #0x1 (1)", - "cfinv" + "sub x20, x4, #0x4 (4)", + "str s18, [x20]", + "mov x27, x10", + "subs w26, w10, #0x1 (1)", + "cfinv", + "mov x10, x26" ] } } diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 143599f9a..923d1fd11 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -12,111 +12,95 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x00", "ExpectedArm64ASM": [ - "mov x20, x7", - "add w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #8", - "eor w27, w20, w5", - "lsl w0, w20, #24", - "cmn w0, w5, lsl #24" + "eor w27, w7, w5", + "lsl w0, w7, #24", + "cmn w0, w5, lsl #24", + "add w26, w7, w5", + "bfxil x7, x26, #0, #8" ] }, "add bx, cx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x01", "ExpectedArm64ASM": [ - "mov x20, x7", - "add w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #16", - "eor w27, w20, w5", - "lsl w0, w20, #16", - "cmn w0, w5, lsl #16" + "eor w27, w7, w5", + "lsl w0, w7, #16", + "cmn w0, w5, lsl #16", + "add w26, w7, w5", + "bfxil x7, x26, #0, #16" ] }, "add ebx, ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ - "mov x20, x7", - "add w7, w20, w5", - "eor w27, w20, w5", - "mov x26, x7", - "cmn w20, w5" + "eor w27, w7, w5", + "adds w26, w7, w5", + "mov x7, x26" ] }, "add rbx, rcx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ - "mov x20, x7", - "add x7, x20, x5", - "eor w27, w20, w5", - "mov x26, x7", - "cmn x20, x5" + "eor w27, w7, w5", + "adds x26, x7, x5", + "mov x7, x26" ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": [ "0x02", "add bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #8", - "eor w27, w20, w7", - "lsl w0, w20, #24", - "cmn w0, w7, lsl #24" + "eor w27, w5, w7", + "lsl w0, w5, #24", + "cmn w0, w7, lsl #24", + "add w26, w5, w7", + "bfxil x5, x26, #0, #8" ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": [ "0x03", "add bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #16", - "eor w27, w20, w7", - "lsl w0, w20, #16", - "cmn w0, w7, lsl #16" + "eor w27, w5, w7", + "lsl w0, w5, #16", + "cmn w0, w7, lsl #16", + "add w26, w5, w7", + "bfxil x5, x26, #0, #16" ] }, "db 0x03, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add w5, w20, w7", - "eor w27, w20, w7", - "mov x26, x5", - "cmn w20, w7" + "eor w27, w5, w7", + "adds w26, w5, w7", + "mov x5, x26" ] }, "db 0x48, 0x03, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add x5, x20, x7", - "eor w27, w20, w7", - "mov x26, x5", - "cmn x20, x7" + "eor w27, w5, w7", + "adds x26, x5, x7", + "mov x5, x26" ] }, "add al, 1": { @@ -125,11 +109,11 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #24", + "cmn w0, w20, lsl #24", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #8", - "lsl w0, w27, #24", - "cmn w0, w20, lsl #24" + "bfxil x4, x26, #0, #8" ] }, "add ax, 1": { @@ -138,83 +122,73 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x1 (1)", - "mov x26, x4", - "cmn w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)", + "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x1 (1)", - "mov x26, x4", - "cmn x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)", + "mov x4, x26" ] }, "add al, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "add w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "eor w27, w4, #0xff", + "lsl w0, w4, #24", + "cmn w0, w20, lsl #24", + "add w26, w4, #0xff (255)", + "bfxil x4, x26, #0, #8" ] }, "add ax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "mov x21, x4", - "add w26, w21, w20", - "mov x4, x21", - "bfxil x4, x26, #0, #16", - "eor w27, w21, #0xffff", - "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "eor w27, w4, #0xffff", + "lsl w0, w4, #16", + "cmn w0, w20, lsl #16", + "add w26, w4, w20", + "bfxil x4, x26, #0, #16" ] }, "add eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "add w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmn w21, w20" + "eor w27, w4, w20", + "adds w26, w4, w20", + "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, #0x1 (1)", - "eor w27, w21, w20", - "mov x26, x4", - "cmn x21, x20" + "eor w27, w4, w20", + "adds x26, x4, x20", + "mov x4, x26" ] }, "or bl, bh": { @@ -1091,16 +1065,16 @@ "ExpectedInstructionCount": 2, "Comment": "0x21", "ExpectedArm64ASM": [ - "ands w7, w7, w5", - "mov x26, x7" + "ands w26, w7, w5", + "mov x7, x26" ] }, "and rbx, rcx": { "ExpectedInstructionCount": 2, "Comment": "0x21", "ExpectedArm64ASM": [ - "ands x7, x7, x5", - "mov x26, x7" + "ands x26, x7, x5", + "mov x7, x26" ] }, "db 0x22, 0xcb": { @@ -1134,8 +1108,8 @@ "and ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "ands w5, w5, w7", - "mov x26, x5" + "ands w26, w5, w7", + "mov x5, x26" ] }, "db 0x48, 0x23, 0xcb": { @@ -1145,8 +1119,8 @@ "and rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "ands x5, x5, x7", - "mov x26, x5" + "ands x26, x5, x7", + "mov x5, x26" ] }, "and al, 1": { @@ -1171,16 +1145,16 @@ "ExpectedInstructionCount": 2, "Comment": "0x25", "ExpectedArm64ASM": [ - "ands w4, w4, #0x1", - "mov x26, x4" + "ands w26, w4, #0x1", + "mov x4, x26" ] }, "and rax, 1": { "ExpectedInstructionCount": 2, "Comment": "0x25", "ExpectedArm64ASM": [ - "ands x4, x4, #0x1", - "mov x26, x4" + "ands x26, x4, #0x1", + "mov x4, x26" ] }, "and al, -1": { @@ -1206,8 +1180,8 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "ands w4, w4, w20", - "mov x26, x4" + "ands w26, w4, w20", + "mov x4, x26" ] }, "and rax, -1": { @@ -1215,124 +1189,108 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "ands x4, x4, x20", - "mov x26, x4" + "ands x26, x4, x20", + "mov x4, x26" ] }, "sub bl, cl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x28", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #8", - "eor w27, w20, w5", - "lsl w0, w20, #24", + "eor w27, w7, w5", + "lsl w0, w7, #24", "cmp w0, w5, lsl #24", - "cfinv" + "sub w26, w7, w5", + "cfinv", + "bfxil x7, x26, #0, #8" ] }, "sub bx, cx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x29", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #16", - "eor w27, w20, w5", - "lsl w0, w20, #16", + "eor w27, w7, w5", + "lsl w0, w7, #16", "cmp w0, w5, lsl #16", - "cfinv" + "sub w26, w7, w5", + "cfinv", + "bfxil x7, x26, #0, #16" ] }, "sub ebx, ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x29", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub w7, w20, w5", - "eor w27, w20, w5", - "mov x26, x7", - "cmp w20, w5", - "cfinv" + "eor w27, w7, w5", + "subs w26, w7, w5", + "cfinv", + "mov x7, x26" ] }, "sub rbx, rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x29", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub x7, x20, x5", - "eor w27, w20, w5", - "mov x26, x7", - "cmp x20, x5", - "cfinv" + "eor w27, w7, w5", + "subs x26, x7, x5", + "cfinv", + "mov x7, x26" ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #8", - "eor w27, w20, w7", - "lsl w0, w20, #24", + "eor w27, w5, w7", + "lsl w0, w5, #24", "cmp w0, w7, lsl #24", - "cfinv" + "sub w26, w5, w7", + "cfinv", + "bfxil x5, x26, #0, #8" ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #16", - "eor w27, w20, w7", - "lsl w0, w20, #16", + "eor w27, w5, w7", + "lsl w0, w5, #16", "cmp w0, w7, lsl #16", - "cfinv" + "sub w26, w5, w7", + "cfinv", + "bfxil x5, x26, #0, #16" ] }, "db 0x2B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub w5, w20, w7", - "eor w27, w20, w7", - "mov x26, x5", - "cmp w20, w7", - "cfinv" + "eor w27, w5, w7", + "subs w26, w5, w7", + "cfinv", + "mov x5, x26" ] }, "db 0x48, 0x2B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub x5, x20, x7", - "eor w27, w20, w7", - "mov x26, x5", - "cmp x20, x7", - "cfinv" + "eor w27, w5, w7", + "subs x26, x5, x7", + "cfinv", + "mov x5, x26" ] }, "sub al, 1": { @@ -1341,12 +1299,12 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "mov x4, x27", - "bfxil x4, x26, #0, #8", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", - "cfinv" + "sub w26, w27, #0x1 (1)", + "cfinv", + "mov x4, x27", + "bfxil x4, x26, #0, #8" ] }, "sub ax, 1": { @@ -1355,90 +1313,80 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "mov x4, x27", - "bfxil x4, x26, #0, #16", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", - "cfinv" + "sub w26, w27, #0x1 (1)", + "cfinv", + "mov x4, x27", + "bfxil x4, x26, #0, #16" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x1 (1)", - "mov x26, x4", - "cmp w27, #0x1 (1)", - "cfinv" + "subs w26, w27, #0x1 (1)", + "cfinv", + "mov x4, x26" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x1 (1)", - "mov x26, x4", - "cmp x27, #0x1 (1)", - "cfinv" + "subs x26, x27, #0x1 (1)", + "cfinv", + "mov x4, x26" ] }, "sub al, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "sub w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", + "eor w27, w4, #0xff", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "cfinv" + "sub w26, w4, #0xff (255)", + "cfinv", + "bfxil x4, x26, #0, #8" ] }, "sub ax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "mov x21, x4", - "sub w26, w21, w20", - "mov x4, x21", - "bfxil x4, x26, #0, #16", - "eor w27, w21, #0xffff", - "lsl w0, w21, #16", + "eor w27, w4, #0xffff", + "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "cfinv" + "sub w26, w4, w20", + "cfinv", + "bfxil x4, x26, #0, #16" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "sub w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp w21, w20", - "cfinv" + "eor w27, w4, w20", + "subs w26, w4, w20", + "cfinv", + "mov x4, x26" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, x20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp x21, x20", - "cfinv" + "eor w27, w4, w20", + "subs x26, x4, x20", + "cfinv", + "mov x4, x26" ] }, "xor bl, cl": { @@ -1565,10 +1513,10 @@ "ExpectedInstructionCount": 5, "Comment": "0x38", "ExpectedArm64ASM": [ - "sub w26, w7, w5", "eor w27, w7, w5", "lsl w0, w7, #24", "cmp w0, w5, lsl #24", + "sub w26, w7, w5", "cfinv" ] }, @@ -1614,30 +1562,28 @@ "ExpectedInstructionCount": 5, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub w26, w7, w5", "eor w27, w7, w5", "lsl w0, w7, #16", "cmp w0, w5, lsl #16", + "sub w26, w7, w5", "cfinv" ] }, "cmp ebx, ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub w26, w7, w5", "eor w27, w7, w5", - "cmp w7, w5", + "subs w26, w7, w5", "cfinv" ] }, "cmp rbx, rcx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub x26, x7, x5", "eor w27, w7, w5", - "cmp x7, x5", + "subs x26, x7, x5", "cfinv" ] }, @@ -1648,10 +1594,10 @@ "cmp bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub w26, w5, w7", "eor w27, w5, w7", "lsl w0, w5, #24", "cmp w0, w7, lsl #24", + "sub w26, w5, w7", "cfinv" ] }, @@ -1662,36 +1608,34 @@ "cmp bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub w26, w5, w7", "eor w27, w5, w7", "lsl w0, w5, #16", "cmp w0, w7, lsl #16", + "sub w26, w5, w7", "cfinv" ] }, "db 0x3B, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub w26, w5, w7", "eor w27, w5, w7", - "cmp w5, w7", + "subs w26, w5, w7", "cfinv" ] }, "db 0x48, 0x3B, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub x26, x5, x7", "eor w27, w5, w7", - "cmp x5, x7", + "subs x26, x5, x7", "cfinv" ] }, @@ -1701,9 +1645,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "cfinv" ] }, @@ -1713,29 +1657,27 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "cfinv" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "cfinv" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x26, x27, #0x1 (1)", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "cfinv" ] }, @@ -1744,10 +1686,10 @@ "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0xff", - "sub w26, w4, #0xff (255)", "eor w27, w4, #0xff", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", + "sub w26, w4, #0xff (255)", "cfinv" ] }, @@ -1756,32 +1698,30 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "sub w26, w4, w20", "eor w27, w4, #0xffff", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", + "sub w26, w4, w20", "cfinv" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "sub w26, w4, w20", "eor w27, w4, w20", - "cmp w4, w20", + "subs w26, w4, w20", "cfinv" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x26, x4, x20", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "cfinv" ] }, @@ -2062,7 +2002,6 @@ "ExpectedArm64ASM": [ "ldrb w20, [x11]", "ldrb w21, [x10]", - "sub w26, w21, w20", "ldrb w22, [x28, #714]", "mov w23, #0x1", "sub x22, x23, x22, lsl #1", @@ -2071,6 +2010,7 @@ "eor w27, w21, w20", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", + "sub w26, w21, w20", "cfinv" ] }, @@ -2082,7 +2022,6 @@ "ExpectedArm64ASM": [ "ldrh w20, [x11]", "ldrh w21, [x10]", - "sub w26, w21, w20", "ldrb w22, [x28, #714]", "mov w23, #0x2", "sub x22, x23, x22, lsl #2", @@ -2091,44 +2030,43 @@ "eor w27, w21, w20", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", + "sub w26, w21, w20", "cfinv" ] }, "cmpsd": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr w20, [x11]", "ldr w21, [x10]", - "sub w26, w21, w20", "ldrb w22, [x28, #714]", "mov w23, #0x4", "sub x22, x23, x22, lsl #3", "add x11, x11, x22", "add x10, x10, x22", "eor w27, w21, w20", - "cmp w21, w20", + "subs w26, w21, w20", "cfinv" ] }, "cmpsq": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr x20, [x11]", "ldr x21, [x10]", - "sub x26, x21, x20", "ldrb w22, [x28, #714]", "mov w23, #0x8", "sub x22, x23, x22, lsl #4", "add x11, x11, x22", "add x10, x10, x22", "eor w27, w21, w20", - "cmp x21, x20", + "subs x26, x21, x20", "cfinv" ] }, @@ -2142,10 +2080,10 @@ "cbz x5, #+0x34", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2164,10 +2102,10 @@ "cbz x5, #+0x34", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2177,45 +2115,43 @@ ] }, "repz cmpsd": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x30", + "cbz x5, #+0x2c", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x2c" + "cbnz w21, #-0x28" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x30", + "cbz x5, #+0x2c", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp x22, x21", + "subs x26, x22, x21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x2c" + "cbnz w21, #-0x28" ] }, "repnz cmpsb": { @@ -2228,10 +2164,10 @@ "cbz x5, #+0x34", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2250,10 +2186,10 @@ "cbz x5, #+0x34", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2263,45 +2199,43 @@ ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x30", + "cbz x5, #+0x2c", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x2c" + "cbz w21, #-0x28" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x30", + "cbz x5, #+0x2c", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp x22, x21", + "subs x26, x22, x21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x2c" + "cbz w21, #-0x28" ] }, "test al, 1": { @@ -2370,7 +2304,6 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "ldrb w21, [x11]", - "sub w26, w20, w21", "ldrb w22, [x28, #714]", "mov w23, #0x1", "sub x22, x23, x22, lsl #1", @@ -2378,6 +2311,7 @@ "eor w27, w20, w21", "lsl w0, w20, #24", "cmp w0, w21, lsl #24", + "sub w26, w20, w21", "cfinv" ] }, @@ -2387,7 +2321,6 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "ldrh w21, [x11]", - "sub w26, w20, w21", "ldrb w22, [x28, #714]", "mov w23, #0x2", "sub x22, x23, x22, lsl #2", @@ -2395,37 +2328,36 @@ "eor w27, w20, w21", "lsl w0, w20, #16", "cmp w0, w21, lsl #16", + "sub w26, w20, w21", "cfinv" ] }, "scasd": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0xaf", "ExpectedArm64ASM": [ "mov w20, w4", "ldr w21, [x11]", - "sub w26, w20, w21", "ldrb w22, [x28, #714]", "mov w23, #0x4", "sub x22, x23, x22, lsl #3", "add x11, x11, x22", "eor w27, w20, w21", - "cmp w20, w21", + "subs w26, w20, w21", "cfinv" ] }, "scasq": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr x20, [x11]", - "sub x26, x4, x20", "ldrb w21, [x28, #714]", "mov w22, #0x8", "sub x21, x22, x21, lsl #4", "add x11, x11, x21", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "cfinv" ] }, @@ -2439,10 +2371,10 @@ "cbz x5, #+0x30", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #24", "cmp w0, w22, lsl #24", + "sub w26, w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2460,10 +2392,10 @@ "cbz x5, #+0x30", "uxth w21, w4", "ldrh w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #16", "cmp w0, w22, lsl #16", + "sub w26, w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2472,37 +2404,17 @@ ] }, "repz scasd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x2c", + "cbz x5, #+0x28", "mov w21, w4", "ldr w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", - "cmp w21, w22", - "cfinv", - "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", - "cset w21, eq", - "cbnz w21, #-0x28" - ] - }, - "repz scasq": { - "ExpectedInstructionCount": 13, - "Comment": "0xaf", - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #714]", - "mov w21, #0x8", - "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x28", - "ldr x21, [x11]", - "sub x26, x4, x21", - "eor w27, w4, w21", - "cmp x4, x21", + "subs w26, w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2510,6 +2422,24 @@ "cbnz w21, #-0x24" ] }, + "repz scasq": { + "ExpectedInstructionCount": 12, + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x24", + "ldr x21, [x11]", + "eor w27, w4, w21", + "subs x26, x4, x21", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "cset w21, eq", + "cbnz w21, #-0x20" + ] + }, "repnz scasb": { "ExpectedInstructionCount": 15, "Comment": "0xae", @@ -2520,10 +2450,10 @@ "cbz x5, #+0x30", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #24", "cmp w0, w22, lsl #24", + "sub w26, w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2541,10 +2471,10 @@ "cbz x5, #+0x30", "uxth w21, w4", "ldrh w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #16", "cmp w0, w22, lsl #16", + "sub w26, w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2553,37 +2483,17 @@ ] }, "repnz scasd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x2c", + "cbz x5, #+0x28", "mov w21, w4", "ldr w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", - "cmp w21, w22", - "cfinv", - "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", - "cset w21, eq", - "cbz w21, #-0x28" - ] - }, - "repnz scasq": { - "ExpectedInstructionCount": 13, - "Comment": "0xaf", - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #714]", - "mov w21, #0x8", - "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x28", - "ldr x21, [x11]", - "sub x26, x4, x21", - "eor w27, w4, w21", - "cmp x4, x21", + "subs w26, w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", @@ -2591,6 +2501,24 @@ "cbz w21, #-0x24" ] }, + "repnz scasq": { + "ExpectedInstructionCount": 12, + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x24", + "ldr x21, [x11]", + "eor w27, w4, w21", + "subs x26, x4, x21", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "cset w21, eq", + "cbz w21, #-0x20" + ] + }, "cmc": { "ExpectedInstructionCount": 1, "Comment": "0xf5", diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 5afa1a7cf..5de4fb65c 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -17,11 +17,11 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #24", + "cmn w0, w20, lsl #24", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #8", - "lsl w0, w27, #24", - "cmn w0, w20, lsl #24" + "bfxil x4, x26, #0, #8" ] }, "or al, 1": { @@ -98,12 +98,12 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "mov x4, x27", - "bfxil x4, x26, #0, #8", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", - "cfinv" + "sub w26, w27, #0x1 (1)", + "cfinv", + "mov x4, x27", + "bfxil x4, x26, #0, #8" ] }, "xor al, 1": { @@ -121,24 +121,22 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "cfinv" ] }, "add al, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "add w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "eor w27, w4, #0xff", + "lsl w0, w4, #24", + "cmn w0, w20, lsl #24", + "add w26, w4, #0xff (255)", + "bfxil x4, x26, #0, #8" ] }, "or al, -1": { @@ -212,18 +210,16 @@ ] }, "sub al, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "sub w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", + "eor w27, w4, #0xff", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "cfinv" + "sub w26, w4, #0xff (255)", + "cfinv", + "bfxil x4, x26, #0, #8" ] }, "xor al, -1": { @@ -240,10 +236,10 @@ "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0xff", - "sub w26, w4, #0xff (255)", "eor w27, w4, #0xff", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", + "sub w26, w4, #0xff (255)", "cfinv" ] }, @@ -253,31 +249,29 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, #0x100 (256)", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x100 (256)", - "mov x26, x4", - "cmn w27, #0x100 (256)" + "adds w26, w27, #0x100 (256)", + "mov x4, x26" ] }, "add rax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x100 (256)", - "mov x26, x4", - "cmn x27, #0x100 (256)" + "adds x26, x27, #0x100 (256)", + "mov x4, x26" ] }, "or eax, 256": { @@ -358,38 +352,36 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands w4, w4, #0x100", - "mov x26, x4" + "ands w26, w4, #0x100", + "mov x4, x26" ] }, "and rax, 256": { "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands x4, x4, #0x100", - "mov x26, x4" + "ands x26, x4, #0x100", + "mov x4, x26" ] }, "sub eax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x100 (256)", - "mov x26, x4", - "cmp w27, #0x100 (256)", - "cfinv" + "subs w26, w27, #0x100 (256)", + "cfinv", + "mov x4, x26" ] }, "sub rax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x100 (256)", - "mov x26, x4", - "cmp x27, #0x100 (256)", - "cfinv" + "subs x26, x27, #0x100 (256)", + "cfinv", + "mov x4, x26" ] }, "xor eax, 256": { @@ -411,22 +403,20 @@ ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w26, w27, #0x100 (256)", - "cmp w27, #0x100 (256)", + "subs w26, w27, #0x100 (256)", "cfinv" ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x26, x27, #0x100 (256)", - "cmp x27, #0x100 (256)", + "subs x26, x27, #0x100 (256)", "cfinv" ] }, @@ -436,33 +426,31 @@ "ExpectedArm64ASM": [ "mov w20, #0xff00", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, w20", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "add w4, w27, w20", - "mov x26, x4", - "cmn w27, w20" + "adds w26, w27, w20", + "mov x4, x26" ] }, "add rax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "sub x4, x27, #0x100 (256)", - "mov x26, x4", - "cmn x27, x20" + "adds x26, x27, x20", + "mov x4, x26" ] }, "or eax, -256": { @@ -543,40 +531,38 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands w4, w4, #0xffffff00", - "mov x26, x4" + "ands w26, w4, #0xffffff00", + "mov x4, x26" ] }, "and rax, -256": { "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands x4, x4, #0xffffffffffffff00", - "mov x26, x4" + "ands x26, x4, #0xffffffffffffff00", + "mov x4, x26" ] }, "sub eax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "sub w4, w27, w20", - "mov x26, x4", - "cmp w27, w20", - "cfinv" + "subs w26, w27, w20", + "cfinv", + "mov x4, x26" ] }, "sub rax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "sub x4, x27, x20", - "mov x26, x4", - "cmp x27, x20", - "cfinv" + "subs x26, x27, x20", + "cfinv", + "mov x4, x26" ] }, "xor eax, -256": { @@ -598,24 +584,22 @@ ] }, "cmp eax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "sub w26, w27, w20", - "cmp w27, w20", + "subs w26, w27, w20", "cfinv" ] }, "cmp rax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "sub x26, x27, x20", - "cmp x27, x20", + "subs x26, x27, x20", "cfinv" ] }, @@ -625,31 +609,29 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x1 (1)", - "mov x26, x4", - "cmn w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)", + "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x1 (1)", - "mov x26, x4", - "cmn x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)", + "mov x4, x26" ] }, "or eax, 1": { @@ -730,38 +712,36 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ - "ands w4, w4, #0x1", - "mov x26, x4" + "ands w26, w4, #0x1", + "mov x4, x26" ] }, "and rax, 1": { "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ - "ands x4, x4, #0x1", - "mov x26, x4" + "ands x26, x4, #0x1", + "mov x4, x26" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x1 (1)", - "mov x26, x4", - "cmp w27, #0x1 (1)", - "cfinv" + "subs w26, w27, #0x1 (1)", + "cfinv", + "mov x4, x26" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x1 (1)", - "mov x26, x4", - "cmp x27, #0x1 (1)", - "cfinv" + "subs x26, x27, #0x1 (1)", + "cfinv", + "mov x4, x26" ] }, "xor eax, 1": { @@ -783,61 +763,53 @@ ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "cfinv" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x26, x27, #0x1 (1)", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "cfinv" ] }, "add ax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "mov x21, x4", - "add w26, w21, w20", - "mov x4, x21", - "bfxil x4, x26, #0, #16", - "eor w27, w21, #0xffff", - "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "eor w27, w4, #0xffff", + "lsl w0, w4, #16", + "cmn w0, w20, lsl #16", + "add w26, w4, w20", + "bfxil x4, x26, #0, #16" ] }, "add eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "add w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmn w21, w20" + "eor w27, w4, w20", + "adds w26, w4, w20", + "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, #0x1 (1)", - "eor w27, w21, w20", - "mov x26, x4", - "cmn x21, x20" + "eor w27, w4, w20", + "adds x26, x4, x20", + "mov x4, x26" ] }, "or eax, -1": { @@ -925,8 +897,8 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "ands w4, w4, w20", - "mov x26, x4" + "ands w26, w4, w20", + "mov x4, x26" ] }, "and rax, -1": { @@ -934,34 +906,30 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "ands x4, x4, x20", - "mov x26, x4" + "ands x26, x4, x20", + "mov x4, x26" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "sub w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp w21, w20", - "cfinv" + "eor w27, w4, w20", + "subs w26, w4, w20", + "cfinv", + "mov x4, x26" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, x20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp x21, x20", - "cfinv" + "eor w27, w4, w20", + "subs x26, x4, x20", + "cfinv", + "mov x4, x26" ] }, "xor eax, -1": { @@ -985,24 +953,22 @@ ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "sub w26, w4, w20", "eor w27, w4, w20", - "cmp w4, w20", + "subs w26, w4, w20", "cfinv" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x26, x4, x20", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "cfinv" ] }, @@ -2239,10 +2205,10 @@ "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "uxtb w27, w7", - "neg w26, w27", - "bfxil x7, x26, #0, #8", "cmp wzr, w27, lsl #24", - "cfinv" + "neg w26, w27", + "cfinv", + "bfxil x7, x26, #0, #8" ] }, "mul bl": { @@ -2357,32 +2323,30 @@ "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "uxth w27, w7", - "neg w26, w27", - "bfxil x7, x26, #0, #16", "cmp wzr, w27, lsl #16", - "cfinv" + "neg w26, w27", + "cfinv", + "bfxil x7, x26, #0, #16" ] }, "neg ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov w27, w7", - "neg w7, w27", - "mov x26, x7", - "cmp wzr, w27", - "cfinv" + "negs w26, w27", + "cfinv", + "mov x7, x26" ] }, "neg rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "neg x7, x27", - "mov x26, x7", - "cmp xzr, x27", - "cfinv" + "negs x26, x27", + "cfinv", + "mov x7, x26" ] }, "mul bx": { @@ -2489,12 +2453,12 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxtb w27, w4", - "add w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #8", "cset w21, hs", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", - "rmif x21, #63, #nzCv" + "add w26, w27, #0x1 (1)", + "rmif x21, #63, #nzCv", + "bfxil x4, x26, #0, #8" ] }, "dec al": { @@ -2503,12 +2467,12 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxtb w27, w4", - "sub w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #8", "cset w21, hs", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", - "rmif x21, #63, #nzCv" + "sub w26, w27, #0x1 (1)", + "rmif x21, #63, #nzCv", + "bfxil x4, x26, #0, #8" ] }, "inc ax": { @@ -2517,36 +2481,34 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxth w27, w4", - "add w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #16", "cset w21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", - "rmif x21, #63, #nzCv" + "add w26, w27, #0x1 (1)", + "rmif x21, #63, #nzCv", + "bfxil x4, x26, #0, #16" ] }, "inc eax": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmn w27, #0x1 (1)", - "rmif x20, #63, #nzCv" + "adds w26, w27, #0x1 (1)", + "rmif x20, #63, #nzCv", + "mov x4, x26" ] }, "inc rax": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmn x27, #0x1 (1)", - "rmif x20, #63, #nzCv" + "adds x26, x27, #0x1 (1)", + "rmif x20, #63, #nzCv", + "mov x4, x26" ] }, "dec ax": { @@ -2555,36 +2517,34 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxth w27, w4", - "sub w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #16", "cset w21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", - "rmif x21, #63, #nzCv" + "sub w26, w27, #0x1 (1)", + "rmif x21, #63, #nzCv", + "bfxil x4, x26, #0, #16" ] }, "dec eax": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmp w27, #0x1 (1)", - "rmif x20, #63, #nzCv" + "subs w26, w27, #0x1 (1)", + "rmif x20, #63, #nzCv", + "mov x4, x26" ] }, "dec rax": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmp x27, #0x1 (1)", - "rmif x20, #63, #nzCv" + "subs x26, x27, #0x1 (1)", + "rmif x20, #63, #nzCv", + "mov x4, x26" ] } } diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index acf53989a..cfc67d905 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1026,10 +1026,10 @@ "uxtb w20, w7", "uxtb w21, w5", "uxtb x22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "cfinv", "bfxil x4, x21, #0, #8", "csel x20, x20, x21, eq", @@ -1042,10 +1042,10 @@ "uxth w20, w7", "uxth w21, w5", "uxth x22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "cfinv", "bfxil x4, x21, #0, #16", "csel x20, x20, x21, eq", @@ -1053,42 +1053,39 @@ ] }, "cmpxchg ecx, ebx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w5", "mov w22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "cfinv", "csel x4, x4, x21, eq", "csel x5, x20, x5, eq" ] }, "cmpxchg rcx, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "ExpectedArm64ASM": [ "mov x20, x5", - "sub x26, x4, x20", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "cfinv", "mov x4, x20", "csel x5, x7, x20, eq" ] }, "cmpxchg [rax], rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x4", "mov x1, x20", "casal x1, x7, [x20]", "mov x4, x1", - "sub x26, x20, x4", "eor w27, w20, w4", - "cmp x20, x4", + "subs x26, x20, x4", "cfinv" ] }, @@ -1099,10 +1096,10 @@ "uxtb w20, w7", "uxtb w21, w4", "uxtb x22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "cfinv", "bfxil x4, x20, #0, #8" ] @@ -1117,10 +1114,10 @@ "casalb w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #8", - "sub w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", + "sub w26, w21, w20", "cfinv" ] }, @@ -1131,10 +1128,10 @@ "uxth w20, w7", "uxth w21, w4", "uxth x22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "cfinv", "bfxil x4, x20, #0, #16" ] @@ -1149,29 +1146,28 @@ "casalh w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #16", - "sub w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", + "sub w26, w21, w20", "cfinv" ] }, "cmpxchg eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w4", "mov w22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "cfinv", "mov x4, x20" ] }, "cmpxchg [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1181,20 +1177,18 @@ "mov w20, w1", "cmp w20, w21", "csel x4, x4, x20, eq", - "sub w26, w21, w20", "eor w27, w21, w20", - "cmp w21, w20", + "subs w26, w21, w20", "cfinv" ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x7", - "sub x26, x4, x4", "mov w27, #0x0", - "cmp x4, x4", + "subs x26, x4, x4", "cfinv", "mov x4, x20" ] @@ -1530,12 +1524,12 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "uxtb w21, w7", - "add w26, w20, w21", - "bfxil x7, x20, #0, #8", - "bfxil x4, x26, #0, #8", "eor w27, w20, w21", "lsl w0, w20, #24", - "cmn w0, w21, lsl #24" + "cmn w0, w21, lsl #24", + "add w26, w20, w21", + "bfxil x7, x20, #0, #8", + "bfxil x4, x26, #0, #8" ] }, "xadd [rax], bl": { @@ -1545,10 +1539,10 @@ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w21, w20" ] }, "xadd ax, bx": { @@ -1557,12 +1551,12 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "uxth w21, w7", - "add w26, w20, w21", - "bfxil x7, x20, #0, #16", - "bfxil x4, x26, #0, #16", "eor w27, w20, w21", "lsl w0, w20, #16", - "cmn w0, w21, lsl #16" + "cmn w0, w21, lsl #16", + "add w26, w20, w21", + "bfxil x7, x20, #0, #16", + "bfxil x4, x26, #0, #16" ] }, "xadd [rax], bx": { @@ -1572,58 +1566,53 @@ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w21, w20" ] }, "xadd eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w4", "mov w21, w7", - "add w4, w20, w21", - "mov x7, x20", "eor w27, w20, w21", - "mov x26, x4", - "cmn w20, w21" + "adds w26, w20, w21", + "mov x7, x20", + "mov x4, x26" ] }, "xadd [rax], ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w26, w7, w20", "eor w27, w7, w20", - "cmn w7, w20" + "adds w26, w7, w20" ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x4", - "mov x21, x7", - "add x4, x20, x21", + "eor w27, w20, w7", + "adds x26, x20, x7", "mov x7, x20", - "eor w27, w20, w21", - "mov x26, x4", - "cmn x20, x21" + "mov x4, x26" ] }, "xadd [rax], rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x26, x7, x20", "eor w27, w7, w20", - "cmn x7, x20" + "adds x26, x7, x20" ] }, "pmovmskb eax, mm0": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index d9ee2d145..5962675a2 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -11,111 +11,95 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x00", "ExpectedArm64ASM": [ - "mov x20, x7", - "add w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #8", - "eor w27, w20, w5", - "lsl w0, w20, #24", - "cmn w0, w5, lsl #24" + "eor w27, w7, w5", + "lsl w0, w7, #24", + "cmn w0, w5, lsl #24", + "add w26, w7, w5", + "bfxil x7, x26, #0, #8" ] }, "add bx, cx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x01", "ExpectedArm64ASM": [ - "mov x20, x7", - "add w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #16", - "eor w27, w20, w5", - "lsl w0, w20, #16", - "cmn w0, w5, lsl #16" + "eor w27, w7, w5", + "lsl w0, w7, #16", + "cmn w0, w5, lsl #16", + "add w26, w7, w5", + "bfxil x7, x26, #0, #16" ] }, "add ebx, ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ - "mov x20, x7", - "add w7, w20, w5", - "eor w27, w20, w5", - "mov x26, x7", - "cmn w20, w5" + "eor w27, w7, w5", + "adds w26, w7, w5", + "mov x7, x26" ] }, "add rbx, rcx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x01", "ExpectedArm64ASM": [ - "mov x20, x7", - "add x7, x20, x5", - "eor w27, w20, w5", - "mov x26, x7", - "cmn x20, x5" + "eor w27, w7, w5", + "adds x26, x7, x5", + "mov x7, x26" ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": [ "0x02", "add bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #8", - "eor w27, w20, w7", - "lsl w0, w20, #24", - "cmn w0, w7, lsl #24" + "eor w27, w5, w7", + "lsl w0, w5, #24", + "cmn w0, w7, lsl #24", + "add w26, w5, w7", + "bfxil x5, x26, #0, #8" ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": [ "0x03", "add bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #16", - "eor w27, w20, w7", - "lsl w0, w20, #16", - "cmn w0, w7, lsl #16" + "eor w27, w5, w7", + "lsl w0, w5, #16", + "cmn w0, w7, lsl #16", + "add w26, w5, w7", + "bfxil x5, x26, #0, #16" ] }, "db 0x03, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add w5, w20, w7", - "eor w27, w20, w7", - "mov x26, x5", - "cmn w20, w7" + "eor w27, w5, w7", + "adds w26, w5, w7", + "mov x5, x26" ] }, "db 0x48, 0x03, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "add x5, x20, x7", - "eor w27, w20, w7", - "mov x26, x5", - "cmn x20, x7" + "eor w27, w5, w7", + "adds x26, x5, x7", + "mov x5, x26" ] }, "add al, 1": { @@ -124,11 +108,11 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #24", + "cmn w0, w20, lsl #24", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #8", - "lsl w0, w27, #24", - "cmn w0, w20, lsl #24" + "bfxil x4, x26, #0, #8" ] }, "add ax, 1": { @@ -137,83 +121,73 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x1 (1)", - "mov x26, x4", - "cmn w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)", + "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x1 (1)", - "mov x26, x4", - "cmn x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)", + "mov x4, x26" ] }, "add al, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "add w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "eor w27, w4, #0xff", + "lsl w0, w4, #24", + "cmn w0, w20, lsl #24", + "add w26, w4, #0xff (255)", + "bfxil x4, x26, #0, #8" ] }, "add ax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "mov x21, x4", - "add w26, w21, w20", - "mov x4, x21", - "bfxil x4, x26, #0, #16", - "eor w27, w21, #0xffff", - "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "eor w27, w4, #0xffff", + "lsl w0, w4, #16", + "cmn w0, w20, lsl #16", + "add w26, w4, w20", + "bfxil x4, x26, #0, #16" ] }, "add eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "add w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmn w21, w20" + "eor w27, w4, w20", + "adds w26, w4, w20", + "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, #0x1 (1)", - "eor w27, w21, w20", - "mov x26, x4", - "cmn x21, x20" + "eor w27, w4, w20", + "adds x26, x4, x20", + "mov x4, x26" ] }, "or bl, bh": { @@ -1138,16 +1112,16 @@ "ExpectedInstructionCount": 2, "Comment": "0x21", "ExpectedArm64ASM": [ - "ands w7, w7, w5", - "mov x26, x7" + "ands w26, w7, w5", + "mov x7, x26" ] }, "and rbx, rcx": { "ExpectedInstructionCount": 2, "Comment": "0x21", "ExpectedArm64ASM": [ - "ands x7, x7, x5", - "mov x26, x7" + "ands x26, x7, x5", + "mov x7, x26" ] }, "db 0x22, 0xcb": { @@ -1181,8 +1155,8 @@ "and ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "ands w5, w5, w7", - "mov x26, x5" + "ands w26, w5, w7", + "mov x5, x26" ] }, "db 0x48, 0x23, 0xcb": { @@ -1192,8 +1166,8 @@ "and rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "ands x5, x5, x7", - "mov x26, x5" + "ands x26, x5, x7", + "mov x5, x26" ] }, "and al, 1": { @@ -1218,16 +1192,16 @@ "ExpectedInstructionCount": 2, "Comment": "0x25", "ExpectedArm64ASM": [ - "ands w4, w4, #0x1", - "mov x26, x4" + "ands w26, w4, #0x1", + "mov x4, x26" ] }, "and rax, 1": { "ExpectedInstructionCount": 2, "Comment": "0x25", "ExpectedArm64ASM": [ - "ands x4, x4, #0x1", - "mov x26, x4" + "ands x26, x4, #0x1", + "mov x4, x26" ] }, "and al, -1": { @@ -1253,8 +1227,8 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "ands w4, w4, w20", - "mov x26, x4" + "ands w26, w4, w20", + "mov x4, x26" ] }, "and rax, -1": { @@ -1262,139 +1236,123 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "ands x4, x4, x20", - "mov x26, x4" + "ands x26, x4, x20", + "mov x4, x26" ] }, "sub bl, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x28", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #8", - "eor w27, w20, w5", - "lsl w0, w20, #24", + "eor w27, w7, w5", + "lsl w0, w7, #24", "cmp w0, w5, lsl #24", + "sub w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x7, x26, #0, #8", "msr nzcv, x20" ] }, "sub bx, cx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x29", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub w26, w20, w5", - "mov x7, x20", - "bfxil x7, x26, #0, #16", - "eor w27, w20, w5", - "lsl w0, w20, #16", + "eor w27, w7, w5", + "lsl w0, w7, #16", "cmp w0, w5, lsl #16", + "sub w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x7, x26, #0, #16", "msr nzcv, x20" ] }, "sub ebx, ecx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x29", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub w7, w20, w5", - "eor w27, w20, w5", - "mov x26, x7", - "cmp w20, w5", + "eor w27, w7, w5", + "subs w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x7, x26", "msr nzcv, x20" ] }, "sub rbx, rcx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x29", "ExpectedArm64ASM": [ - "mov x20, x7", - "sub x7, x20, x5", - "eor w27, w20, w5", - "mov x26, x7", - "cmp x20, x5", + "eor w27, w7, w5", + "subs x26, x7, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x7, x26", "msr nzcv, x20" ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #8", - "eor w27, w20, w7", - "lsl w0, w20, #24", + "eor w27, w5, w7", + "lsl w0, w5, #24", "cmp w0, w7, lsl #24", + "sub w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x5, x26, #0, #8", "msr nzcv, x20" ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub w26, w20, w7", - "mov x5, x20", - "bfxil x5, x26, #0, #16", - "eor w27, w20, w7", - "lsl w0, w20, #16", + "eor w27, w5, w7", + "lsl w0, w5, #16", "cmp w0, w7, lsl #16", + "sub w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x5, x26, #0, #16", "msr nzcv, x20" ] }, "db 0x2B, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub w5, w20, w7", - "eor w27, w20, w7", - "mov x26, x5", - "cmp w20, w7", + "eor w27, w5, w7", + "subs w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x5, x26", "msr nzcv, x20" ] }, "db 0x48, 0x2B, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "mov x20, x5", - "sub x5, x20, x7", - "eor w27, w20, w7", - "mov x26, x5", - "cmp x20, x7", + "eor w27, w5, w7", + "subs x26, x5, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x5, x26", "msr nzcv, x20" ] }, @@ -1404,13 +1362,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "mov x4, x27", - "bfxil x4, x26, #0, #8", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x27", + "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, @@ -1420,103 +1378,93 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "mov x4, x27", - "bfxil x4, x26, #0, #16", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x27", + "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x1 (1)", - "mov x26, x4", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x1 (1)", - "mov x26, x4", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub al, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "sub w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", + "eor w27, w4, #0xff", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", + "sub w26, w4, #0xff (255)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "sub ax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "mov x21, x4", - "sub w26, w21, w20", - "mov x4, x21", - "bfxil x4, x26, #0, #16", - "eor w27, w21, #0xffff", - "lsl w0, w21, #16", + "eor w27, w4, #0xffff", + "lsl w0, w4, #16", "cmp w0, w20, lsl #16", + "sub w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "sub w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp w21, w20", + "eor w27, w4, w20", + "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, x20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp x21, x20", + "eor w27, w4, w20", + "subs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, @@ -1644,10 +1592,10 @@ "ExpectedInstructionCount": 7, "Comment": "0x38", "ExpectedArm64ASM": [ - "sub w26, w7, w5", "eor w27, w7, w5", "lsl w0, w7, #24", "cmp w0, w5, lsl #24", + "sub w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1695,34 +1643,32 @@ "ExpectedInstructionCount": 7, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub w26, w7, w5", "eor w27, w7, w5", "lsl w0, w7, #16", "cmp w0, w5, lsl #16", + "sub w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp ebx, ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub w26, w7, w5", "eor w27, w7, w5", - "cmp w7, w5", + "subs w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rbx, rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub x26, x7, x5", "eor w27, w7, w5", - "cmp x7, x5", + "subs x26, x7, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1735,10 +1681,10 @@ "cmp bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub w26, w5, w7", "eor w27, w5, w7", "lsl w0, w5, #24", "cmp w0, w7, lsl #24", + "sub w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1751,40 +1697,38 @@ "cmp bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub w26, w5, w7", "eor w27, w5, w7", "lsl w0, w5, #16", "cmp w0, w7, lsl #16", + "sub w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "db 0x3B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub w26, w5, w7", "eor w27, w5, w7", - "cmp w5, w7", + "subs w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "db 0x48, 0x3B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub x26, x5, x7", "eor w27, w5, w7", - "cmp x5, x7", + "subs x26, x5, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1796,9 +1740,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1810,33 +1754,31 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x26, x27, #0x1 (1)", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1847,10 +1789,10 @@ "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0xff", - "sub w26, w4, #0xff (255)", "eor w27, w4, #0xff", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", + "sub w26, w4, #0xff (255)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1861,36 +1803,34 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "sub w26, w4, w20", "eor w27, w4, #0xffff", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", + "sub w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "sub w26, w4, w20", "eor w27, w4, w20", - "cmp w4, w20", + "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x26, x4, x20", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -3160,7 +3100,6 @@ "ExpectedArm64ASM": [ "ldrb w20, [x11]", "ldrb w21, [x10]", - "sub w26, w21, w20", "ldrb w22, [x28, #714]", "mov w23, #0x1", "sub x22, x23, x22, lsl #1", @@ -3169,6 +3108,7 @@ "eor w27, w21, w20", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", + "sub w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -3182,7 +3122,6 @@ "ExpectedArm64ASM": [ "ldrh w20, [x11]", "ldrh w21, [x10]", - "sub w26, w21, w20", "ldrb w22, [x28, #714]", "mov w23, #0x2", "sub x22, x23, x22, lsl #2", @@ -3191,48 +3130,47 @@ "eor w27, w21, w20", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", + "sub w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmpsd": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr w20, [x11]", "ldr w21, [x10]", - "sub w26, w21, w20", "ldrb w22, [x28, #714]", "mov w23, #0x4", "sub x22, x23, x22, lsl #3", "add x11, x11, x22", "add x10, x10, x22", "eor w27, w21, w20", - "cmp w21, w20", + "subs w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmpsq": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr x20, [x11]", "ldr x21, [x10]", - "sub x26, x21, x20", "ldrb w22, [x28, #714]", "mov w23, #0x8", "sub x22, x23, x22, lsl #4", "add x11, x11, x22", "add x10, x10, x22", "eor w27, w21, w20", - "cmp x21, x20", + "subs x26, x21, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -3248,10 +3186,10 @@ "cbz x5, #+0x3c", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3272,10 +3210,10 @@ "cbz x5, #+0x3c", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3287,18 +3225,17 @@ ] }, "repz cmpsd": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x38", + "cbz x5, #+0x34", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3306,22 +3243,21 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x34" + "cbnz w21, #-0x30" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x38", + "cbz x5, #+0x34", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp x22, x21", + "subs x26, x22, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3329,7 +3265,7 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x34" + "cbnz w21, #-0x30" ] }, "repnz cmpsb": { @@ -3342,10 +3278,10 @@ "cbz x5, #+0x3c", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3366,10 +3302,10 @@ "cbz x5, #+0x3c", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3381,18 +3317,17 @@ ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x38", + "cbz x5, #+0x34", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w26, w22, w21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3400,22 +3335,21 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x34" + "cbz w21, #-0x30" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x38", + "cbz x5, #+0x34", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp x22, x21", + "subs x26, x22, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3423,7 +3357,7 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x34" + "cbz w21, #-0x30" ] }, "test al, 1": { @@ -3738,7 +3672,6 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "ldrb w21, [x11]", - "sub w26, w20, w21", "ldrb w22, [x28, #714]", "mov w23, #0x1", "sub x22, x23, x22, lsl #1", @@ -3746,6 +3679,7 @@ "eor w27, w20, w21", "lsl w0, w20, #24", "cmp w0, w21, lsl #24", + "sub w26, w20, w21", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -3757,7 +3691,6 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "ldrh w21, [x11]", - "sub w26, w20, w21", "ldrb w22, [x28, #714]", "mov w23, #0x2", "sub x22, x23, x22, lsl #2", @@ -3765,41 +3698,40 @@ "eor w27, w20, w21", "lsl w0, w20, #16", "cmp w0, w21, lsl #16", + "sub w26, w20, w21", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "scasd": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Comment": "0xaf", "ExpectedArm64ASM": [ "mov w20, w4", "ldr w21, [x11]", - "sub w26, w20, w21", "ldrb w22, [x28, #714]", "mov w23, #0x4", "sub x22, x23, x22, lsl #3", "add x11, x11, x22", "eor w27, w20, w21", - "cmp w20, w21", + "subs w26, w20, w21", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "scasq": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr x20, [x11]", - "sub x26, x4, x20", "ldrb w21, [x28, #714]", "mov w22, #0x8", "sub x21, x22, x21, lsl #4", "add x11, x11, x21", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -3815,10 +3747,10 @@ "cbz x5, #+0x38", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #24", "cmp w0, w22, lsl #24", + "sub w26, w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3838,10 +3770,10 @@ "cbz x5, #+0x38", "uxth w21, w4", "ldrh w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #16", "cmp w0, w22, lsl #16", + "sub w26, w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3852,39 +3784,17 @@ ] }, "repz scasd": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x34", + "cbz x5, #+0x30", "mov w21, w4", "ldr w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", - "cmp w21, w22", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", - "cset w21, eq", - "cbnz w21, #-0x30" - ] - }, - "repz scasq": { - "ExpectedInstructionCount": 15, - "Comment": "0xaf", - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #714]", - "mov w21, #0x8", - "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x30", - "ldr x21, [x11]", - "sub x26, x4, x21", - "eor w27, w4, w21", - "cmp x4, x21", + "subs w26, w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3894,6 +3804,26 @@ "cbnz w21, #-0x2c" ] }, + "repz scasq": { + "ExpectedInstructionCount": 14, + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x2c", + "ldr x21, [x11]", + "eor w27, w4, w21", + "subs x26, x4, x21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "cset w21, eq", + "cbnz w21, #-0x28" + ] + }, "repnz scasb": { "ExpectedInstructionCount": 17, "Comment": "0xae", @@ -3904,10 +3834,10 @@ "cbz x5, #+0x38", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #24", "cmp w0, w22, lsl #24", + "sub w26, w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3927,10 +3857,10 @@ "cbz x5, #+0x38", "uxth w21, w4", "ldrh w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", "lsl w0, w21, #16", "cmp w0, w22, lsl #16", + "sub w26, w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3941,39 +3871,17 @@ ] }, "repnz scasd": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x34", + "cbz x5, #+0x30", "mov w21, w4", "ldr w22, [x11]", - "sub w26, w21, w22", "eor w27, w21, w22", - "cmp w21, w22", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", - "cset w21, eq", - "cbz w21, #-0x30" - ] - }, - "repnz scasq": { - "ExpectedInstructionCount": 15, - "Comment": "0xaf", - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #714]", - "mov w21, #0x8", - "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x30", - "ldr x21, [x11]", - "sub x26, x4, x21", - "eor w27, w4, w21", - "cmp x4, x21", + "subs w26, w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -3983,6 +3891,26 @@ "cbz w21, #-0x2c" ] }, + "repnz scasq": { + "ExpectedInstructionCount": 14, + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x2c", + "ldr x21, [x11]", + "eor w27, w4, w21", + "subs x26, x4, x21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "cset w21, eq", + "cbz w21, #-0x28" + ] + }, "mov al, 0xff": { "ExpectedInstructionCount": 1, "Comment": "0xb0", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index d0cb9c68b..891d608f8 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -20,11 +20,11 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #24", + "cmn w0, w20, lsl #24", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #8", - "lsl w0, w27, #24", - "cmn w0, w20, lsl #24" + "bfxil x4, x26, #0, #8" ] }, "or al, 1": { @@ -103,13 +103,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "mov x4, x27", - "bfxil x4, x26, #0, #8", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x27", + "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, @@ -128,26 +128,24 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "sub w26, w27, #0x1 (1)", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add al, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "add w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "eor w27, w4, #0xff", + "lsl w0, w4, #24", + "cmn w0, w20, lsl #24", + "add w26, w4, #0xff (255)", + "bfxil x4, x26, #0, #8" ] }, "or al, -1": { @@ -223,19 +221,17 @@ ] }, "sub al, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", - "mov x21, x4", - "sub w26, w21, #0xff (255)", - "mov x4, x21", - "bfxil x4, x26, #0, #8", - "eor w27, w21, #0xff", - "lsl w0, w21, #24", + "eor w27, w4, #0xff", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", + "sub w26, w4, #0xff (255)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, @@ -253,10 +249,10 @@ "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0xff", - "sub w26, w4, #0xff (255)", "eor w27, w4, #0xff", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", + "sub w26, w4, #0xff (255)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -268,31 +264,29 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, #0x100 (256)", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x100 (256)", - "mov x26, x4", - "cmn w27, #0x100 (256)" + "adds w26, w27, #0x100 (256)", + "mov x4, x26" ] }, "add rax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x100 (256)", - "mov x26, x4", - "cmn x27, #0x100 (256)" + "adds x26, x27, #0x100 (256)", + "mov x4, x26" ] }, "or eax, 256": { @@ -381,41 +375,39 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands w4, w4, #0x100", - "mov x26, x4" + "ands w26, w4, #0x100", + "mov x4, x26" ] }, "and rax, 256": { "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands x4, x4, #0x100", - "mov x26, x4" + "ands x26, x4, #0x100", + "mov x4, x26" ] }, "sub eax, 256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x100 (256)", - "mov x26, x4", - "cmp w27, #0x100 (256)", + "subs w26, w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub rax, 256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x100 (256)", - "mov x26, x4", - "cmp x27, #0x100 (256)", + "subs x26, x27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, @@ -438,24 +430,22 @@ ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w26, w27, #0x100 (256)", - "cmp w27, #0x100 (256)", + "subs w26, w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x26, x27, #0x100 (256)", - "cmp x27, #0x100 (256)", + "subs x26, x27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -467,33 +457,31 @@ "ExpectedArm64ASM": [ "mov w20, #0xff00", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, w20", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "add w4, w27, w20", - "mov x26, x4", - "cmn w27, w20" + "adds w26, w27, w20", + "mov x4, x26" ] }, "add rax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "sub x4, x27, #0x100 (256)", - "mov x26, x4", - "cmn x27, x20" + "adds x26, x27, x20", + "mov x4, x26" ] }, "or eax, -256": { @@ -582,43 +570,41 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands w4, w4, #0xffffff00", - "mov x26, x4" + "ands w26, w4, #0xffffff00", + "mov x4, x26" ] }, "and rax, -256": { "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ - "ands x4, x4, #0xffffffffffffff00", - "mov x26, x4" + "ands x26, x4, #0xffffffffffffff00", + "mov x4, x26" ] }, "sub eax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "sub w4, w27, w20", - "mov x26, x4", - "cmp w27, w20", + "subs w26, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub rax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "sub x4, x27, x20", - "mov x26, x4", - "cmp x27, x20", + "subs x26, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, @@ -641,26 +627,24 @@ ] }, "cmp eax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "sub w26, w27, w20", - "cmp w27, w20", + "subs w26, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "sub x26, x27, x20", - "cmp x27, x20", + "subs x26, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -672,31 +656,29 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", + "lsl w0, w27, #16", + "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", "mov x4, x27", - "bfxil x4, x26, #0, #16", - "lsl w0, w27, #16", - "cmn w0, w20, lsl #16" + "bfxil x4, x26, #0, #16" ] }, "add eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x1 (1)", - "mov x26, x4", - "cmn w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)", + "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x1 (1)", - "mov x26, x4", - "cmn x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)", + "mov x4, x26" ] }, "or eax, 1": { @@ -785,41 +767,39 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ - "ands w4, w4, #0x1", - "mov x26, x4" + "ands w26, w4, #0x1", + "mov x4, x26" ] }, "and rax, 1": { "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ - "ands x4, x4, #0x1", - "mov x26, x4" + "ands x26, x4, #0x1", + "mov x4, x26" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x1 (1)", - "mov x26, x4", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x1 (1)", - "mov x26, x4", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, @@ -842,65 +822,57 @@ ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w26, w27, #0x1 (1)", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x26, x27, #0x1 (1)", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add ax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "mov x21, x4", - "add w26, w21, w20", - "mov x4, x21", - "bfxil x4, x26, #0, #16", - "eor w27, w21, #0xffff", - "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "eor w27, w4, #0xffff", + "lsl w0, w4, #16", + "cmn w0, w20, lsl #16", + "add w26, w4, w20", + "bfxil x4, x26, #0, #16" ] }, "add eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "add w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmn w21, w20" + "eor w27, w4, w20", + "adds w26, w4, w20", + "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, #0x1 (1)", - "eor w27, w21, w20", - "mov x26, x4", - "cmn x21, x20" + "eor w27, w4, w20", + "adds x26, x4, x20", + "mov x4, x26" ] }, "or eax, -1": { @@ -996,8 +968,8 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "ands w4, w4, w20", - "mov x26, x4" + "ands w26, w4, w20", + "mov x4, x26" ] }, "and rax, -1": { @@ -1005,37 +977,33 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "ands x4, x4, x20", - "mov x26, x4" + "ands x26, x4, x20", + "mov x4, x26" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "mov x21, x4", - "sub w4, w21, w20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp w21, w20", + "eor w27, w4, w20", + "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "mov x21, x4", - "sub x4, x21, x20", - "eor w27, w21, w20", - "mov x26, x4", - "cmp x21, x20", + "eor w27, w4, w20", + "subs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x4, x26", "msr nzcv, x20" ] }, @@ -1060,26 +1028,24 @@ ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "sub w26, w4, w20", "eor w27, w4, w20", - "cmp w4, w20", + "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x26, x4, x20", "eor w27, w4, w20", - "cmp x4, x20", + "subs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -2697,11 +2663,11 @@ "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "uxtb w27, w7", - "neg w26, w27", - "bfxil x7, x26, #0, #8", "cmp wzr, w27, lsl #24", + "neg w26, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x7, x26, #0, #8", "msr nzcv, x20" ] }, @@ -2838,37 +2804,35 @@ "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "uxth w27, w7", - "neg w26, w27", - "bfxil x7, x26, #0, #16", "cmp wzr, w27, lsl #16", + "neg w26, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "bfxil x7, x26, #0, #16", "msr nzcv, x20" ] }, "neg ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov w27, w7", - "neg w7, w27", - "mov x26, x7", - "cmp wzr, w27", + "negs w26, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x7, x26", "msr nzcv, x20" ] }, "neg rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "neg x7, x27", - "mov x26, x7", - "cmp xzr, x27", + "negs x26, x27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", + "mov x7, x26", "msr nzcv, x20" ] }, @@ -3098,13 +3062,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxtb w27, w4", - "add w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #8", "cset w21, hs", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", + "add w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, @@ -3114,13 +3078,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxtb w27, w4", - "sub w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #8", "cset w21, hs", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, @@ -3130,45 +3094,43 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxth w27, w4", - "add w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #16", "cset w21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", + "add w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] }, "inc eax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add w4, w27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmn w27, #0x1 (1)", + "adds w26, w27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", "mov w20, w0", + "mov x4, x26", "msr nzcv, x20" ] }, "inc rax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov x27, x4", - "add x4, x27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmn x27, #0x1 (1)", + "adds x26, x27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", "mov w20, w0", + "mov x4, x26", "msr nzcv, x20" ] }, @@ -3178,45 +3140,43 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxth w27, w4", - "sub w26, w27, #0x1 (1)", - "bfxil x4, x26, #0, #16", "cset w21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] }, "dec eax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov x27, x4", - "sub w4, w27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", "mov w20, w0", + "mov x4, x26", "msr nzcv, x20" ] }, "dec rax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov x27, x4", - "sub x4, x27, #0x1 (1)", - "mov x26, x4", "cset w20, hs", - "cmp x27, #0x1 (1)", + "subs x26, x27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", "mov w20, w0", + "mov x4, x26", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index c740117e6..8ec12ed1b 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -272,29 +272,28 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxth w27, w4", - "add w26, w27, #0x1 (1)", - "bfxil w4, w26, #0, #16", "cset w21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", + "add w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "bfxil w4, w26, #0, #16", "msr nzcv, x20" ] }, "inc eax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x40", "ExpectedArm64ASM": [ "mov w27, w4", - "add w4, w27, #0x1 (1)", - "mov w26, w4", "cset w20, hs", - "cmn w27, #0x1 (1)", + "adds w26, w27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", "mov w20, w0", + "mov w4, w26", "msr nzcv, x20" ] }, @@ -304,13 +303,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "uxth w27, w4", - "sub w26, w27, #0x1 (1)", - "bfxil w4, w26, #0, #16", "cset w21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", + "sub w26, w27, #0x1 (1)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "bfxil w4, w26, #0, #16", "msr nzcv, x20" ] }, @@ -329,18 +328,17 @@ ] }, "dec eax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x48", "ExpectedArm64ASM": [ "mov w27, w4", - "sub w4, w27, #0x1 (1)", - "mov w26, w4", "cset w20, hs", - "cmp w27, #0x1 (1)", + "subs w26, w27, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", "mov w20, w0", + "mov w4, w26", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 3f6ae6e94..a1285b456 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -1888,10 +1888,10 @@ "uxtb w20, w7", "uxtb w21, w4", "uxtb x22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", "lsl w0, w22, #24", "cmp w0, w21, lsl #24", + "sub w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1908,10 +1908,10 @@ "casalb w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #8", - "sub w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", + "sub w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1924,10 +1924,10 @@ "uxth w20, w7", "uxth w21, w4", "uxth x22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", "lsl w0, w22, #16", "cmp w0, w21, lsl #16", + "sub w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1944,25 +1944,24 @@ "casalh w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #16", - "sub w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", + "sub w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmpxchg eax, ebx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w4", "mov w22, w4", - "sub x26, x22, x21", "eor w27, w22, w21", - "cmp w22, w21", + "subs w26, w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1970,7 +1969,7 @@ ] }, "cmpxchg [rax], ebx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1980,22 +1979,20 @@ "mov w20, w1", "cmp w20, w21", "csel x4, x4, x20, eq", - "sub w26, w21, w20", "eor w27, w21, w20", - "cmp w21, w20", + "subs w26, w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x7", - "sub x26, x4, x4", "mov w27, #0x0", - "cmp x4, x4", + "subs x26, x4, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -2003,16 +2000,15 @@ ] }, "cmpxchg [rax], rbx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x4", "mov x1, x20", "casal x1, x7, [x20]", "mov x4, x1", - "sub x26, x20, x4", "eor w27, w20, w4", - "cmp x20, x4", + "subs x26, x20, x4", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -2543,12 +2539,12 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "uxtb w21, w7", - "add w26, w20, w21", - "bfxil x7, x20, #0, #8", - "bfxil x4, x26, #0, #8", "eor w27, w20, w21", "lsl w0, w20, #24", - "cmn w0, w21, lsl #24" + "cmn w0, w21, lsl #24", + "add w26, w20, w21", + "bfxil x7, x20, #0, #8", + "bfxil x4, x26, #0, #8" ] }, "xadd [rax], bl": { @@ -2558,10 +2554,10 @@ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #24", - "cmn w0, w20, lsl #24" + "cmn w0, w20, lsl #24", + "add w26, w21, w20" ] }, "xadd ax, bx": { @@ -2570,12 +2566,12 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "uxth w21, w7", - "add w26, w20, w21", - "bfxil x7, x20, #0, #16", - "bfxil x4, x26, #0, #16", "eor w27, w20, w21", "lsl w0, w20, #16", - "cmn w0, w21, lsl #16" + "cmn w0, w21, lsl #16", + "add w26, w20, w21", + "bfxil x7, x20, #0, #16", + "bfxil x4, x26, #0, #16" ] }, "xadd [rax], bx": { @@ -2585,58 +2581,53 @@ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w26, w21, w20", "eor w27, w21, w20", "lsl w0, w21, #16", - "cmn w0, w20, lsl #16" + "cmn w0, w20, lsl #16", + "add w26, w21, w20" ] }, "xadd eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w4", "mov w21, w7", - "add w4, w20, w21", - "mov x7, x20", "eor w27, w20, w21", - "mov x26, x4", - "cmn w20, w21" + "adds w26, w20, w21", + "mov x7, x20", + "mov x4, x26" ] }, "xadd [rax], ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w26, w7, w20", "eor w27, w7, w20", - "cmn w7, w20" + "adds w26, w7, w20" ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x4", - "mov x21, x7", - "add x4, x20, x21", + "eor w27, w20, w7", + "adds x26, x20, x7", "mov x7, x20", - "eor w27, w20, w21", - "mov x26, x4", - "cmn x20, x21" + "mov x4, x26" ] }, "xadd [rax], rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x26, x7, x20", "eor w27, w7, w20", - "cmn x7, x20" + "adds x26, x7, x20" ] }, "cmpps xmm0, xmm1, 0": {