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Rename BlockCache to LookupCache

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This commit is contained in:
Stefanos Kornilios Mitsis Poiitidis 2021-01-28 13:40:47 +02:00
parent d6ee3caad4
commit 0c9e05ed8f
16 changed files with 75 additions and 75 deletions
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2
External/FEXCore/Source/CMakeLists.txt vendored
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@ -118,7 +118,7 @@ set (SRCS
Common/SoftFloat-3e/s_f32UIToCommonNaN.c
Interface/Config/Config.cpp
Interface/Context/Context.cpp
Interface/Core/BlockCache.cpp
Interface/Core/LookupCache.cpp
Interface/Core/BlockSamplingData.cpp
Interface/Core/CompileService.cpp
Interface/Core/Core.cpp

10
External/FEXCore/Source/Interface/Core/CompileService.cpp vendored
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@ -1,5 +1,5 @@
#include "Interface/Context/Context.h"
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/CompileService.h"
#include "Interface/Core/InternalThreadState.h"
#include "Interface/Core/OpcodeDispatcher.h"
@ -71,7 +71,7 @@ namespace FEXCore {
// Clear the inverse cache of what is calling us from the Context ClearCache routine
auto SelectedThread = Thread->IsCompileService ? ParentThread : Thread;
SelectedThread->BlockCache->ClearCache();
SelectedThread->LookupCache->ClearCache();
SelectedThread->CPUBackend->ClearCache();
SelectedThread->IntBackend->ClearCache();
}
@ -79,7 +79,7 @@ namespace FEXCore {
void CompileService::RemoveCodeEntry(uint64_t GuestRIP) {
CompileThreadData->IRLists.erase(GuestRIP);
CompileThreadData->DebugData.erase(GuestRIP);
CompileThreadData->BlockCache->Erase(GuestRIP);
CompileThreadData->LookupCache->Erase(GuestRIP);
}
CompileService::WorkItem *CompileService::CompileCode(uint64_t RIP) {
@ -133,7 +133,7 @@ namespace FEXCore {
// If we had a work item then work on it
if (Item) {
// Does the block cache already contain this RIP?
void *CompiledCode = reinterpret_cast<void*>(CompileThreadData->BlockCache->FindBlock(Item->RIP));
void *CompiledCode = reinterpret_cast<void*>(CompileThreadData->LookupCache->FindBlock(Item->RIP));
FEXCore::Core::DebugData *DebugData = nullptr;
if (!CompiledCode) {
@ -150,7 +150,7 @@ namespace FEXCore {
ERROR_AND_DIE("Couldn't compile code for thread at RIP: 0x%lx", Item->RIP);
}
auto BlockMapPtr = CompileThreadData->BlockCache->AddBlockMapping(Item->RIP, CompiledCode);
auto BlockMapPtr = CompileThreadData->LookupCache->AddBlockMapping(Item->RIP, CompiledCode);
if (BlockMapPtr == 0) {
// XXX: We currently have the expectation that compiler service block cache will be significantly underutilized compared to regular thread
ERROR_AND_DIE("Couldn't add code to block cache for thread at RIP: 0x%lx", Item->RIP);

18
External/FEXCore/Source/Interface/Core/Core.cpp vendored
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@ -2,7 +2,7 @@
#include "Common/Paths.h"
#include "Interface/Context/Context.h"
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/BlockSamplingData.h"
#include "Interface/Core/CompileService.h"
#include "Interface/Core/Core.h"
@ -494,7 +494,7 @@ namespace FEXCore::Context {
void Context::InitializeCompiler(FEXCore::Core::InternalThreadState* State, bool CompileThread) {
State->OpDispatcher = std::make_unique<FEXCore::IR::OpDispatchBuilder>(this);
State->OpDispatcher->SetMultiblock(Config.Multiblock);
State->BlockCache = std::make_unique<FEXCore::BlockCache>(this);
State->LookupCache = std::make_unique<FEXCore::LookupCache>(this);
State->FrontendDecoder = std::make_unique<FEXCore::Frontend::Decoder>(this);
State->PassManager = std::make_unique<FEXCore::IR::PassManager>();
State->PassManager->RegisterExitHandler([this]() {
@ -560,9 +560,9 @@ namespace FEXCore::Context {
}
uintptr_t Context::AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr) {
auto BlockMapPtr = Thread->BlockCache->AddBlockMapping(Address, Ptr);
auto BlockMapPtr = Thread->LookupCache->AddBlockMapping(Address, Ptr);
if (BlockMapPtr == 0) {
Thread->BlockCache->ClearCache();
Thread->LookupCache->ClearCache();
// Pull out the current IR we added and store it back after we cleared the rest of the list
// Needed in the case the the block mapping has aliased
@ -572,7 +572,7 @@ namespace FEXCore::Context {
Thread->IRLists.clear();
Thread->IRLists.try_emplace(Address, IR);
}
BlockMapPtr = Thread->BlockCache->AddBlockMapping(Address, Ptr);
BlockMapPtr = Thread->LookupCache->AddBlockMapping(Address, Ptr);
LogMan::Throw::A(BlockMapPtr, "Couldn't add mapping after clearing mapping cache");
}
@ -580,7 +580,7 @@ namespace FEXCore::Context {
}
void Context::ClearCodeCache(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
Thread->BlockCache->ClearCache();
Thread->LookupCache->ClearCache();
Thread->CPUBackend->ClearCache();
Thread->IntBackend->ClearCache();
@ -930,7 +930,7 @@ namespace FEXCore::Context {
void Context::RemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
Thread->IRLists.erase(GuestRIP);
Thread->DebugData.erase(GuestRIP);
Thread->BlockCache->Erase(GuestRIP);
Thread->LookupCache->Erase(GuestRIP);
if (Thread->CompileService) {
Thread->CompileService->RemoveCodeEntry(GuestRIP);
@ -945,7 +945,7 @@ namespace FEXCore::Context {
// Erase the RIP from all the storage backings if it exists
Thread->IRLists.erase(RIP);
Thread->DebugData.erase(RIP);
Thread->BlockCache->Erase(RIP);
Thread->LookupCache->Erase(RIP);
// We don't care if compilation passes or not
CompileBlock(Thread, RIP);
@ -976,7 +976,7 @@ namespace FEXCore::Context {
}
bool Context::FindHostCodeForRIP(uint64_t RIP, uint8_t **Code) {
uintptr_t HostCode = ParentThread->BlockCache->FindBlock(RIP);
uintptr_t HostCode = ParentThread->LookupCache->FindBlock(RIP);
if (!HostCode) {
return false;
}

12
External/FEXCore/Source/Interface/Core/Interpreter/Arm64Dispatcher.cpp vendored
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@ -199,13 +199,13 @@ DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Co
auto RipReg = x2;
// Mask the address by the virtual address size so we can check for aliases
LoadConstant(x3, Thread->BlockCache->GetVirtualMemorySize() - 1);
LoadConstant(x3, Thread->LookupCache->GetVirtualMemorySize() - 1);
and_(x3, RipReg, x3);
{
// This is the block cache lookup routine
// It matches what is going on it BlockCache.h::FindBlock
LoadConstant(x0, Thread->BlockCache->GetPagePointer());
// It matches what is going on it LookupCache.h::FindBlock
LoadConstant(x0, Thread->LookupCache->GetPagePointer());
// Offset the address and add to our page pointer
lsr(x1, x3, 12);
@ -220,16 +220,16 @@ DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Co
and_(x1, x3, 0x0FFF);
// Shift the offset by the size of the block cache entry
add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::BlockCache::BlockCacheEntry))));
add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
// Load the guest address first to ensure it maps to the address we are currently at
// This fixes aliasing problems
ldr(x1, MemOperand(x0, offsetof(FEXCore::BlockCache::BlockCacheEntry, GuestCode)));
ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
cmp(x1, RipReg);
b(&NoBlock, Condition::ne);
// Now load the actual host block to execute if we can
ldr(x1, MemOperand(x0, offsetof(FEXCore::BlockCache::BlockCacheEntry, HostCode)));
ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
cbz(x1, &NoBlock);
// If we've made it here then we have a real compiled block

2
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h vendored
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@ -1,6 +1,6 @@
#pragma once
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/InternalThreadState.h"
#include <FEXCore/Core/CPUBackend.h>

2
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp vendored
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@ -5,7 +5,7 @@
#ifdef _M_ARM_64
#include "Interface/Core/ArchHelpers/Arm64.h"
#endif
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/DebugData.h"
#include "Interface/Core/InternalThreadState.h"
#include "Interface/Core/Interpreter/InterpreterClass.h"

6
External/FEXCore/Source/Interface/Core/Interpreter/x86_64Dispatcher.cpp vendored
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@ -94,13 +94,13 @@ DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Co
AbsoluteLoopTopAddress = getCurr<uint64_t>();
{
mov(r13, Thread->BlockCache->GetPagePointer());
mov(r13, Thread->LookupCache->GetPagePointer());
// Load our RIP
mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
mov(rax, rdx);
mov(rbx, Thread->BlockCache->GetVirtualMemorySize() - 1);
mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
and_(rax, rbx);
shr(rax, 12);
@ -113,7 +113,7 @@ DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Co
mov (rax, rdx);
and_(rax, 0x0FFF);
shl(rax, (int)log2(sizeof(FEXCore::BlockCache::BlockCacheEntry)));
shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
// check for aliasing
mov(rcx, qword [rdi + rax + 8]);

4
External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp vendored
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@ -84,9 +84,9 @@ DEF_OP(ExitFunction) {
RipReg = GetReg<RA_64>(Op->Header.Args[0].ID());
// L1 Cache
LoadConstant(x0, State->BlockCache->GetL1Pointer());
LoadConstant(x0, State->LookupCache->GetL1Pointer());
and_(x3, RipReg, BlockCache::L1_ENTRIES_MASK);
and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
add(x0, x0, Operand(x3, Shift::LSL, 4));
ldp(x1, x0, MemOperand(x0));

28
External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp vendored
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@ -1016,7 +1016,7 @@ void JITCore::PopCalleeSavedRegisters() {
uint64_t JITCore::ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadState *Thread, uint64_t *record) {
auto GuestRip = record[1];
auto HostCode = Thread->BlockCache->FindBlock(GuestRip);
auto HostCode = Thread->LookupCache->FindBlock(GuestRip);
if (!HostCode) {
//printf("ExitFunctionLink: Aborting, %lX not in cache\n", GuestRip);
@ -1038,7 +1038,7 @@ uint64_t JITCore::ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadS
vixl::aarch64::CPU::EnsureIAndDCacheCoherency((void*)branch, 24);
// Add de-linking handler
Thread->BlockCache->AddBlockLink(GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
vixl::aarch64::Assembler emit((uint8_t*)(branch), 24);
vixl::CodeBufferCheckScope scope(&emit, 24, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
Literal l_BranchHost{LinkerAddress};
@ -1053,7 +1053,7 @@ uint64_t JITCore::ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadS
record[0] = HostCode;
// Add de-linking handler
Thread->BlockCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
record[0] = LinkerAddress;
});
}
@ -1093,9 +1093,9 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
// }
uint64_t VirtualMemorySize = Thread->BlockCache->GetVirtualMemorySize();
uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
Literal l_VirtualMemory {VirtualMemorySize};
Literal l_PagePtr {Thread->BlockCache->GetPagePointer()};
Literal l_PagePtr {Thread->LookupCache->GetPagePointer()};
Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
Literal l_Interpreter {reinterpret_cast<uint64_t>(State->IntBackend->CompileCode(nullptr, nullptr))};
Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
@ -1169,9 +1169,9 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
auto RipReg = x2;
// L1 Cache
LoadConstant(x0, Thread->BlockCache->GetL1Pointer());
LoadConstant(x0, Thread->LookupCache->GetL1Pointer());
and_(x3, RipReg, BlockCache::L1_ENTRIES_MASK);
and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
add(x0, x0, Operand(x3, Shift::LSL, 4));
ldp(x1, x0, MemOperand(x0));
cmp(x0, RipReg);
@ -1182,12 +1182,12 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
bind(&FullLookup);
// This is the block cache lookup routine
// It matches what is going on it BlockCache.h::FindBlock
// It matches what is going on it LookupCache.h::FindBlock
ldr(x0, &l_PagePtr);
// Mask the address by the virtual address size so we can check for aliases
if (__builtin_popcountl(VirtualMemorySize) == 1) {
and_(x3, RipReg, Thread->BlockCache->GetVirtualMemorySize() - 1);
and_(x3, RipReg, Thread->LookupCache->GetVirtualMemorySize() - 1);
}
else {
ldr(x3, &l_VirtualMemory);
@ -1209,24 +1209,24 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
and_(x1, x3, 0x0FFF);
// Shift the offset by the size of the block cache entry
add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::BlockCache::BlockCacheEntry))));
add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
// Load the guest address first to ensure it maps to the address we are currently at
// This fixes aliasing problems
ldr(x1, MemOperand(x0, offsetof(FEXCore::BlockCache::BlockCacheEntry, GuestCode)));
ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
cmp(x1, RipReg);
b(&NoBlock, Condition::ne);
// Now load the actual host block to execute if we can
ldr(x3, MemOperand(x0, offsetof(FEXCore::BlockCache::BlockCacheEntry, HostCode)));
ldr(x3, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
cbz(x3, &NoBlock);
// If we've made it here then we have a real compiled block
{
// update L1 cache
LoadConstant(x0, Thread->BlockCache->GetL1Pointer());
LoadConstant(x0, Thread->LookupCache->GetL1Pointer());
and_(x1, RipReg, BlockCache::L1_ENTRIES_MASK);
and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
add(x0, x0, Operand(x1, Shift::LSL, 4));
stp(x3, x2, MemOperand(x0));
br(x3);

2
External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h vendored
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@ -1,6 +1,6 @@
#pragma once
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include "aarch64/assembler-aarch64.h"
#include "aarch64/cpu-aarch64.h"

4
External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp vendored
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@ -81,10 +81,10 @@ DEF_OP(ExitFunction) {
Xbyak::Reg RipReg = GetSrc<RA_64>(Op->NewRIP.ID());
// L1 Cache
mov(rcx, ThreadState->BlockCache->GetL1Pointer());
mov(rcx, ThreadState->LookupCache->GetL1Pointer());
mov(rax, RipReg);
and_(rax, BlockCache::L1_ENTRIES_MASK);
and_(rax, LookupCache::L1_ENTRIES_MASK);
shl(rax, 4);
Xbyak::RegExp LookupBase = rcx + rax;

18
External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp vendored
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@ -804,7 +804,7 @@ static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalT
uint64_t JITCore::ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadState *Thread, uint64_t *record) {
auto GuestRip = record[1];
auto HostCode = Thread->BlockCache->FindBlock(GuestRip);
auto HostCode = Thread->LookupCache->FindBlock(GuestRip);
if (!HostCode) {
Thread->State.State.rip = GuestRip;
@ -812,7 +812,7 @@ uint64_t JITCore::ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadS
}
auto LinkerAddress = core->ExitFunctionLinkerAddress;
Thread->BlockCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
// undo the link
record[0] = LinkerAddress;
});
@ -884,21 +884,21 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
// L1 Cache
mov(r13, Thread->BlockCache->GetL1Pointer());
mov(r13, Thread->LookupCache->GetL1Pointer());
mov(rax, rdx);
and_(rax, BlockCache::L1_ENTRIES_MASK);
and_(rax, LookupCache::L1_ENTRIES_MASK);
shl(rax, 4);
cmp(qword[r13 + rax + 8], rdx);
jne(FullLookup);
jmp(qword[r13 + rax + 0]);
L(FullLookup);
mov(r13, Thread->BlockCache->GetPagePointer());
mov(r13, Thread->LookupCache->GetPagePointer());
// Full lookup
mov(rax, rdx);
mov(rbx, Thread->BlockCache->GetVirtualMemorySize() - 1);
mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
and_(rax, rbx);
shr(rax, 12);
@ -911,7 +911,7 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
mov (rax, rdx);
and(rax, 0x0FFF);
shl(rax, (int)log2(sizeof(FEXCore::BlockCache::BlockCacheEntry)));
shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
// check for aliasing
mov(rcx, qword [rdi + rax + 8]);
@ -925,9 +925,9 @@ void JITCore::CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread) {
je(NoBlock);
// Update L1
mov(r13, Thread->BlockCache->GetL1Pointer());
mov(r13, Thread->LookupCache->GetL1Pointer());
mov(rcx, rdx);
and_(rcx, BlockCache::L1_ENTRIES_MASK);
and_(rcx, LookupCache::L1_ENTRIES_MASK);
shl(rcx, 1);
mov(qword[r13 + rcx*8 + 8], rdx);
mov(qword[r13 + rcx*8 + 0], rax);

2
External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h vendored
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@ -1,6 +1,6 @@
#pragma once
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/BlockSamplingData.h"
#include "Interface/Core/JIT/x86_64/JIT.h"

10
External/FEXCore/Source/Interface/Core/BlockCache.cpp → External/FEXCore/Source/Interface/Core/LookupCache.cpp vendored
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@ -1,10 +1,10 @@
#include "Interface/Context/Context.h"
#include "Interface/Core/Core.h"
#include "Interface/Core/BlockCache.h"
#include "Interface/Core/LookupCache.h"
#include <sys/mman.h>
namespace FEXCore {
BlockCache::BlockCache(FEXCore::Context::Context *CTX)
LookupCache::LookupCache(FEXCore::Context::Context *CTX)
: ctx {CTX} {
// Block cache ends up looking like this
@ -36,13 +36,13 @@ BlockCache::BlockCache(FEXCore::Context::Context *CTX)
VirtualMemSize = ctx->Config.VirtualMemSize;
}
BlockCache::~BlockCache() {
LookupCache::~LookupCache() {
munmap(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8);
munmap(reinterpret_cast<void*>(PageMemory), CODE_SIZE);
munmap(reinterpret_cast<void*>(L1Pointer), L1_SIZE);
}
void BlockCache::HintUsedRange(uint64_t Address, uint64_t Size) {
void LookupCache::HintUsedRange(uint64_t Address, uint64_t Size) {
// Tell the kernel we will definitely need [Address, Address+Size) mapped for the page pointer
// Page Pointer is allocated per page, so shift by page size
Address >>= 12;
@ -50,7 +50,7 @@ void BlockCache::HintUsedRange(uint64_t Address, uint64_t Size) {
madvise(reinterpret_cast<void*>(PagePointer + Address), Size, MADV_WILLNEED);
}
void BlockCache::ClearCache() {
void LookupCache::ClearCache() {
// Clear out the page memory
madvise(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8, MADV_DONTNEED);
madvise(reinterpret_cast<void*>(PageMemory), CODE_SIZE, MADV_DONTNEED);

26
External/FEXCore/Source/Interface/Core/BlockCache.h → External/FEXCore/Source/Interface/Core/LookupCache.h vendored
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@ -3,18 +3,18 @@
#include <FEXCore/Utils/LogManager.h>
namespace FEXCore {
class BlockCache {
class LookupCache {
public:
struct BlockCacheEntry {
struct LookupCacheEntry {
uintptr_t HostCode;
uintptr_t GuestCode;
};
BlockCache(FEXCore::Context::Context *CTX);
~BlockCache();
LookupCache(FEXCore::Context::Context *CTX);
~LookupCache();
using BlockCacheIter = uintptr_t;
using LookupCacheIter = uintptr_t;
uintptr_t End() { return 0; }
uintptr_t FindBlock(uint64_t Address) {
@ -31,7 +31,7 @@ public:
}
// Do L1
auto &L1Entry = reinterpret_cast<BlockCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
if (L1Entry.GuestCode == Address) {
L1Entry.GuestCode = L1Entry.HostCode = 0;
}
@ -49,14 +49,14 @@ public:
}
// Page exists, just set the offset to zero
auto BlockPointers = reinterpret_cast<BlockCacheEntry*>(LocalPagePointer);
auto BlockPointers = reinterpret_cast<LookupCacheEntry*>(LocalPagePointer);
BlockPointers[PageOffset].GuestCode = 0;
BlockPointers[PageOffset].HostCode = 0;
}
uintptr_t AddBlockMapping(uint64_t Address, void *Ptr) {
// Do L1
auto &L1Entry = reinterpret_cast<BlockCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
if (L1Entry.GuestCode == Address) {
L1Entry.GuestCode = L1Entry.HostCode = 0;
}
@ -82,7 +82,7 @@ public:
}
// Add the new pointer to the page block
auto BlockPointers = reinterpret_cast<BlockCacheEntry*>(LocalPagePointer);
auto BlockPointers = reinterpret_cast<LookupCacheEntry*>(LocalPagePointer);
uintptr_t CastPtr = reinterpret_cast<uintptr_t>(Ptr);
// This silently replaces existing mappings
@ -125,7 +125,7 @@ private:
uintptr_t FindCodePointerForAddress(uint64_t Address) {
// Do L1
auto &L1Entry = reinterpret_cast<BlockCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
if (L1Entry.GuestCode == Address) {
return L1Entry.HostCode;
}
@ -143,7 +143,7 @@ private:
}
// Find there pointer for the address in the blocks
auto BlockPointers = reinterpret_cast<BlockCacheEntry*>(LocalPagePointer);
auto BlockPointers = reinterpret_cast<LookupCacheEntry*>(LocalPagePointer);
if (BlockPointers[PageOffset].GuestCode == FullAddress)
{
@ -175,8 +175,8 @@ private:
std::map<BlockLinkTag, std::function<void()>> BlockLinks;
constexpr static size_t CODE_SIZE = 128 * 1024 * 1024;
constexpr static size_t SIZE_PER_PAGE = 4096 * sizeof(BlockCacheEntry);
constexpr static size_t L1_SIZE = L1_ENTRIES * sizeof(BlockCacheEntry);
constexpr static size_t SIZE_PER_PAGE = 4096 * sizeof(LookupCacheEntry);
constexpr static size_t L1_SIZE = L1_ENTRIES * sizeof(LookupCacheEntry);
size_t AllocateOffset {};

4
External/FEXCore/include/FEXCore/Debug/InternalThreadState.h vendored
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@ -8,7 +8,7 @@
#include <thread>
namespace FEXCore {
class BlockCache;
class LookupCache;
class CompileService;
}
@ -75,7 +75,7 @@ namespace FEXCore::Core {
std::shared_ptr<FEXCore::CPU::CPUBackend> IntBackend;
std::unique_ptr<FEXCore::CPU::CPUBackend> FallbackBackend;
std::unique_ptr<FEXCore::BlockCache> BlockCache;
std::unique_ptr<FEXCore::LookupCache> LookupCache;
std::unordered_map<uint64_t, std::unique_ptr<FEXCore::IR::IRListView<true>>> IRLists;
std::unordered_map<uint64_t, FEXCore::Core::DebugData> DebugData;