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Merge pull request #2258 from Sonicadvance1/fixed_syscall_spill

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Arm64: Inline Syscall spill optimization
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Mai 2022-12-16 18:48:08 +00:00 committed by GitHub
commit 0ebb15c732
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External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp vendored
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@ -255,10 +255,6 @@ DEF_OP(InlineSyscall) {
Intersects = true;
}
}
// XXX: For some reason spilling only the x4, x5, and x8 registers was causing issues
// Come back to this once investigation reveals why it fails the gvisor ioctl test
// For now override to all GPRs
SpillMask = ~0U;
// Ordering is incredibly important here
// We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all