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OpcodeDispatcher: Handle VPHSUBSW

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This commit is contained in:
Lioncache 2023-02-23 10:36:55 -05:00
parent 052872725c
commit 1045e05870
6 changed files with 133 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5969,6 +5969,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(2, 0b01, 0x05), 1, &OpDispatchBuilder::VPHSUBOp<2>},
{OPD(2, 0b01, 0x06), 1, &OpDispatchBuilder::VPHSUBOp<4>},
{OPD(2, 0b01, 0x07), 1, &OpDispatchBuilder::VPHSUBSWOp},
{OPD(2, 0b01, 0x08), 1, &OpDispatchBuilder::VPSIGN<1>},
{OPD(2, 0b01, 0x09), 1, &OpDispatchBuilder::VPSIGN<2>},

1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
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@ -495,6 +495,7 @@ public:
template <size_t ElementSize>
void VPHSUBOp(OpcodeArgs);
void VPHSUBSWOp(OpcodeArgs);
void VPMADDWDOp(OpcodeArgs);

14
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
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@ -3390,6 +3390,20 @@ void OpDispatchBuilder::PHSUBS(OpcodeArgs) {
StoreResult(FPRClass, Op, Result, -1);
}
void OpDispatchBuilder::VPHSUBSWOp(OpcodeArgs) {
const auto DstSize = GetDstSize(Op);
const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
OrderedNode *Result = PHSUBSOpImpl(Op, Op->Src[0], Op->Src[1]);
OrderedNode *Dest = Result;
if (Is256Bit) {
Dest = _VInsElement(DstSize, 8, 1, 2, Result, Result);
Dest = _VInsElement(DstSize, 8, 2, 1, Dest, Result);
}
StoreResult(FPRClass, Op, Dest, -1);
}
void OpDispatchBuilder::PSADBW(OpcodeArgs) {
// The documentation is actually incorrect in how this instruction operates
// It strongly implies that the `abs(dest[i] - src[i])` operates in 8bit space

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -266,7 +266,7 @@ void InitializeVEXTables() {
{OPD(2, 0b01, 0x04), 1, X86InstInfo{"VPMADDUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x05), 1, X86InstInfo{"VPHSUBW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x06), 1, X86InstInfo{"VPHSUBD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x07), 1, X86InstInfo{"VPHSUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x07), 1, X86InstInfo{"VPHSUBSW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x08), 1, X86InstInfo{"VPSIGNB", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x09), 1, X86InstInfo{"VPSIGNW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},

58
unittests/ASM/VEX/vphsubsw.asm Normal file
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@ -0,0 +1,58 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM4": ["0x0202020202020202", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0x0000000000000000", "0x0202020202020202", "0x0000000000000000", "0x0000000000000000"],
"XMM6": ["0xFF01FF0100FF00FF", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0x0000000000000000", "0xFF01FF0100FF00FF", "0x0000000000000000", "0x0000000000000000"],
"XMM8": ["0x0202020202020202", "0xFF01FF0100FF00FF", "0x0000000000000000", "0x0000000000000000"],
"XMM9": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM10": ["0xFF01FF0100FF00FF", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM11": ["0x800080007FFF7FFF", "0x800080007FFF7FFF", "0x0000000000000000", "0x0000000000000000"]
}
}
%endif
lea rdx, [rel .data]
vmovaps ymm0, [rdx]
vmovaps ymm1, [rdx + 32]
vmovaps ymm2, [rdx + 32 * 2]
vmovaps ymm3, [rdx + 32 * 3]
vphsubsw xmm4, xmm0, [rdx + 32]
vphsubsw xmm5, xmm1, [rdx]
vphsubsw xmm6, xmm2, [rdx + 32]
vphsubsw xmm7, xmm1, [rdx + 32 * 2]
vphsubsw xmm8, xmm0, [rdx + 32 * 2]
vphsubsw xmm9, xmm1, [rdx + 32]
vphsubsw xmm10, xmm2, [rdx + 32]
vphsubsw xmm11, xmm3, [rdx + 32 * 3]
hlt
align 32
.data:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x6162636465666768
dq 0x7172737475767778
dq 0x7F7F7F7F7F7F7F7F
dq 0x8080808080808080
dq 0x8080808080808080
dq 0x7F7F7F7F7F7F7F7F
dq 0x2119221823172416
dq 0x3941384237433644
dq 0x4598654387293847
dq 0x7620937492893892
dq 0x00007FFF00007FFF
dq 0x7FFFFFFF7FFFFFFF
dq 0x7FFFFFFF7FFFFFFF
dq 0x00007FFF00007FFF

58
unittests/ASM/VEX/vphsubsw_256.asm Normal file
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@ -0,0 +1,58 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM4": ["0x0202020202020202", "0x0000000000000000", "0x0202020202020202", "0x0000000000000000"],
"XMM5": ["0x0000000000000000", "0x0202020202020202", "0x0000000000000000", "0x0202020202020202"],
"XMM6": ["0xFF01FF0100FF00FF", "0x0000000000000000", "0x80007FFF1FAB7FFF", "0x0000000000000000"],
"XMM7": ["0x0000000000000000", "0xFF01FF0100FF00FF", "0x0000000000000000", "0x80007FFF1FAB7FFF"],
"XMM8": ["0x0202020202020202", "0xFF01FF0100FF00FF", "0x0202020202020202", "0x80007FFF1FAB7FFF"],
"XMM9": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM10": ["0xFF01FF0100FF00FF", "0x0000000000000000", "0x80007FFF1FAB7FFF", "0x0000000000000000"],
"XMM11": ["0x800080007FFF7FFF", "0x800080007FFF7FFF", "0x7FFF7FFF80008000", "0x7FFF7FFF80008000"]
}
}
%endif
lea rdx, [rel .data]
vmovaps ymm0, [rdx]
vmovaps ymm1, [rdx + 32]
vmovaps ymm2, [rdx + 32 * 2]
vmovaps ymm3, [rdx + 32 * 3]
vphsubsw ymm4, ymm0, [rdx + 32]
vphsubsw ymm5, ymm1, [rdx]
vphsubsw ymm6, ymm2, [rdx + 32]
vphsubsw ymm7, ymm1, [rdx + 32 * 2]
vphsubsw ymm8, ymm0, [rdx + 32 * 2]
vphsubsw ymm9, ymm1, [rdx + 32]
vphsubsw ymm10, ymm2, [rdx + 32]
vphsubsw ymm11, ymm3, [rdx + 32 * 3]
hlt
align 32
.data:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x6162636465666768
dq 0x7172737475767778
dq 0x7F7F7F7F7F7F7F7F
dq 0x8080808080808080
dq 0x8080808080808080
dq 0x7F7F7F7F7F7F7F7F
dq 0x2119221823172416
dq 0x3941384237433644
dq 0x4598654387293847
dq 0x7620937492893892
dq 0x00007FFF00007FFF
dq 0x7FFFFFFF7FFFFFFF
dq 0x7FFFFFFF7FFFFFFF
dq 0x00007FFF00007FFF