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Extends SHLD/SHRD unit tests to ensure Zext behaviour
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24
unittests/ASM/TwoByte/0F_A4_2.asm
Normal file
24
unittests/ASM/TwoByte/0F_A4_2.asm
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@ -0,0 +1,24 @@
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%ifdef CONFIG
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{
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"RegData": {
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"R15": "0xFFFFFFFFFFFFFFFF",
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"R14": "0x4141414141410000",
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"R13": "0",
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"R12": "0",
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"R11": "0x00000000FFFFFFFF"
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}
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}
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%endif
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mov r15, -1
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mov r14, 0x4141414141410000
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mov r13, 0
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mov r12, 0
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mov r11, -1
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shld r14w, r15w, 0
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shld r13d, r15d, 0
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shld r12, r15, 0
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shld r11d, r15d, 0
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hlt
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@ -4,7 +4,8 @@
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"R15": "0xFFFFFFFFFFFFFFFF",
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"R14": "0x4141414141410000",
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"R13": "0",
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"R12": "0"
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"R12": "0",
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"R11": "0x00000000FFFFFFFF"
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}
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}
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%endif
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@ -14,9 +15,11 @@ mov r15, -1
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mov r14, 0x4141414141410000
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mov r13, 0
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mov r12, 0
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mov r11, -1
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shld r14w, r15w, cl
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shld r13d, r15d, cl
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shld r12, r15, cl
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shld r11d, r15d, cl
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hlt
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24
unittests/ASM/TwoByte/0F_AC_2.asm
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24
unittests/ASM/TwoByte/0F_AC_2.asm
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@ -0,0 +1,24 @@
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%ifdef CONFIG
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{
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"RegData": {
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"R15": "0xFFFFFFFFFFFFFFFF",
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"R14": "0x4141414141410000",
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"R13": "0",
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"R12": "0",
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"R11": "0x00000000FFFFFFFF"
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}
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}
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%endif
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mov r15, -1
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mov r14, 0x4141414141410000
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mov r13, 0
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mov r12, 0
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mov r11, -1
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shrd r14w, r15w, 0
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shrd r13d, r15d, 0
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shrd r12, r15, 0
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shrd r11d, r15d, 0
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hlt
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@ -4,7 +4,8 @@
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"R15": "0xFFFFFFFFFFFFFFFF",
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"R14": "0x4141414141410000",
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"R13": "0",
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"R12": "0"
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"R12": "0",
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"R11": "0x00000000FFFFFFFF"
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}
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}
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%endif
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@ -14,9 +15,11 @@ mov r15, -1
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mov r14, 0x4141414141410000
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mov r13, 0
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mov r12, 0
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mov r11, -1
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shrd r14w, r15w, cl
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shrd r13d, r15d, cl
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shrd r12, r15, cl
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shrd r11d, r15d, cl
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hlt
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