mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-02-12 18:39:18 +00:00
Update InstCountCI
This commit is contained in:
Billy Laws
parent
d490cb1b79
commit
12fb26f9c0
@ -216,7 +216,7 @@
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]
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},
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"positive rep movsb": {
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"ExpectedInstructionCount": 42,
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"ExpectedInstructionCount": 44,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -232,10 +232,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x70",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x54",
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"cbz x0, #+0x78",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x54",
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"sub x0, x0, #0x20 (32)",
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"tbnz x0, #63, #+0x44",
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"sub x0, x0, #0x20 (32)",
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@ -271,7 +273,7 @@
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]
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},
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"positive rep movsw": {
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"ExpectedInstructionCount": 42,
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"ExpectedInstructionCount": 44,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -287,10 +289,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x70",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x54",
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"cbz x0, #+0x78",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x54",
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"sub x0, x0, #0x10 (16)",
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"tbnz x0, #63, #+0x44",
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"sub x0, x0, #0x10 (16)",
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@ -326,7 +330,7 @@
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]
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},
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"positive rep movsd": {
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"ExpectedInstructionCount": 42,
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"ExpectedInstructionCount": 44,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -342,10 +346,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x70",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x54",
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"cbz x0, #+0x78",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x54",
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"sub x0, x0, #0x8 (8)",
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"tbnz x0, #63, #+0x44",
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"sub x0, x0, #0x8 (8)",
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@ -381,7 +387,7 @@
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]
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},
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"positive rep movsq": {
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"ExpectedInstructionCount": 42,
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"ExpectedInstructionCount": 44,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -397,10 +403,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x70",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x54",
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"cbz x0, #+0x78",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x54",
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"sub x0, x0, #0x4 (4)",
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"tbnz x0, #63, #+0x44",
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"sub x0, x0, #0x4 (4)",
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@ -436,7 +444,7 @@
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]
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},
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"negative rep movsb": {
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"ExpectedInstructionCount": 45,
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"ExpectedInstructionCount": 47,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -451,10 +459,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x80",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x64",
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"cbz x0, #+0x88",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x64",
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"sub x1, x1, #0x1f (31)",
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"sub x2, x2, #0x1f (31)",
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"sub x0, x0, #0x20 (32)",
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@ -494,7 +504,7 @@
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]
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},
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"negative rep movsw": {
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"ExpectedInstructionCount": 45,
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"ExpectedInstructionCount": 47,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -509,10 +519,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x80",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x64",
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"cbz x0, #+0x88",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x64",
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"sub x1, x1, #0x1e (30)",
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"sub x2, x2, #0x1e (30)",
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"sub x0, x0, #0x10 (16)",
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@ -552,7 +564,7 @@
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]
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},
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"negative rep movsd": {
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"ExpectedInstructionCount": 45,
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"ExpectedInstructionCount": 47,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -567,10 +579,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x80",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x64",
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"cbz x0, #+0x88",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x64",
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"sub x1, x1, #0x1c (28)",
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"sub x2, x2, #0x1c (28)",
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"sub x0, x0, #0x8 (8)",
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@ -610,7 +624,7 @@
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]
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},
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"negative rep movsq": {
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"ExpectedInstructionCount": 45,
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"ExpectedInstructionCount": 47,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -625,10 +639,12 @@
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"mov x0, x5",
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"mov x1, x11",
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"mov x2, x10",
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"cbz x0, #+0x80",
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"orr x3, x1, x2",
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"and x3, x3, #0x3",
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"cbnz x3, #+0x64",
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"cbz x0, #+0x88",
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"sub x3, x1, x2",
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"tbz x3, #63, #+0x8",
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"neg x3, x3",
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"sub x3, x3, #0x20 (32)",
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"tbnz x3, #63, #+0x64",
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"sub x1, x1, #0x18 (24)",
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"sub x2, x2, #0x18 (24)",
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"sub x0, x0, #0x4 (4)",
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@ -668,7 +684,7 @@
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]
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},
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"positive rep stosb": {
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"ExpectedInstructionCount": 32,
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"ExpectedInstructionCount": 30,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -684,9 +700,7 @@
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"uxtb w21, w4",
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"mov x0, x5",
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"mov x1, x11",
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"cbz x0, #+0x60",
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"and x3, x1, #0x3",
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"cbnz x3, #+0x4c",
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"cbz x0, #+0x58",
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"sub x0, x0, #0x20 (32)",
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"tbnz x0, #63, #+0x3c",
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"dup v1.16b, w21",
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@ -713,7 +727,7 @@
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]
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},
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"positive rep stosw": {
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"ExpectedInstructionCount": 32,
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"ExpectedInstructionCount": 30,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -729,9 +743,7 @@
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"uxth w21, w4",
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"mov x0, x5",
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"mov x1, x11",
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"cbz x0, #+0x60",
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"and x3, x1, #0x3",
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"cbnz x3, #+0x4c",
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"cbz x0, #+0x58",
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"sub x0, x0, #0x10 (16)",
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"tbnz x0, #63, #+0x3c",
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"dup v1.8h, w21",
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@ -758,7 +770,7 @@
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]
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},
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"positive rep stosd": {
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"ExpectedInstructionCount": 32,
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"ExpectedInstructionCount": 30,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -774,9 +786,7 @@
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"mov w21, w4",
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"mov x0, x5",
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"mov x1, x11",
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"cbz x0, #+0x60",
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"and x3, x1, #0x3",
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"cbnz x3, #+0x4c",
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"cbz x0, #+0x58",
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"sub x0, x0, #0x8 (8)",
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"tbnz x0, #63, #+0x3c",
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"dup v1.4s, w21",
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@ -803,7 +813,7 @@
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]
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},
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"positive rep stosq": {
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"ExpectedInstructionCount": 31,
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"ExpectedInstructionCount": 29,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
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"loads and stores can turn in to post-increment when known"
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@ -818,9 +828,7 @@
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"strb w21, [x28, #714]",
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"mov x0, x5",
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"mov x1, x11",
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"cbz x0, #+0x60",
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"and x3, x1, #0x3",
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"cbnz x3, #+0x4c",
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"cbz x0, #+0x58",
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"sub x0, x0, #0x4 (4)",
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"tbnz x0, #63, #+0x3c",
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"dup v1.2d, x4",
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@ -847,7 +855,7 @@
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]
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},
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"negative rep stosb": {
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"ExpectedInstructionCount": 33,
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"ExpectedInstructionCount": 31,
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"Comment": [
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"When direction flag is a compile time constant we can optimize",
|
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"loads and stores can turn in to post-increment when known"
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@ -862,9 +870,7 @@
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"uxtb w20, w4",
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"mov x0, x5",
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"mov x1, x11",
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"cbz x0, #+0x68",
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"and x3, x1, #0x3",
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"cbnz x3, #+0x54",
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"cbz x0, #+0x60",
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"sub x1, x1, #0x1f (31)",
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"sub x0, x0, #0x20 (32)",
|
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"tbnz x0, #63, #+0x3c",
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@ -893,7 +899,7 @@
|
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]
|
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},
|
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"negative rep stosw": {
|
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"ExpectedInstructionCount": 33,
|
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"ExpectedInstructionCount": 31,
|
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"Comment": [
|
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"When direction flag is a compile time constant we can optimize",
|
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"loads and stores can turn in to post-increment when known"
|
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@ -908,9 +914,7 @@
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"uxth w20, w4",
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"mov x0, x5",
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"mov x1, x11",
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"cbz x0, #+0x68",
|
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"and x3, x1, #0x3",
|
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"cbnz x3, #+0x54",
|
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"cbz x0, #+0x60",
|
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"sub x1, x1, #0x1e (30)",
|
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"sub x0, x0, #0x10 (16)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
@ -939,7 +943,7 @@
|
||||
]
|
||||
},
|
||||
"negative rep stosd": {
|
||||
"ExpectedInstructionCount": 33,
|
||||
"ExpectedInstructionCount": 31,
|
||||
"Comment": [
|
||||
"When direction flag is a compile time constant we can optimize",
|
||||
"loads and stores can turn in to post-increment when known"
|
||||
@ -954,9 +958,7 @@
|
||||
"mov w20, w4",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"cbz x0, #+0x68",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"cbz x0, #+0x60",
|
||||
"sub x1, x1, #0x1c (28)",
|
||||
"sub x0, x0, #0x8 (8)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
@ -985,7 +987,7 @@
|
||||
]
|
||||
},
|
||||
"negative rep stosq": {
|
||||
"ExpectedInstructionCount": 32,
|
||||
"ExpectedInstructionCount": 30,
|
||||
"Comment": [
|
||||
"When direction flag is a compile time constant we can optimize",
|
||||
"loads and stores can turn in to post-increment when known"
|
||||
@ -999,9 +1001,7 @@
|
||||
"strb w20, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"cbz x0, #+0x68",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"cbz x0, #+0x60",
|
||||
"sub x1, x1, #0x18 (24)",
|
||||
"sub x0, x0, #0x4 (4)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
|
||||
@ -2860,18 +2860,20 @@
|
||||
]
|
||||
},
|
||||
"rep movsb": {
|
||||
"ExpectedInstructionCount": 79,
|
||||
"ExpectedInstructionCount": 83,
|
||||
"Comment": "0xa4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrsb x20, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"mov x2, x10",
|
||||
"tbnz w20, #1, #+0x8c",
|
||||
"cbz x0, #+0x70",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"tbnz w20, #1, #+0x94",
|
||||
"cbz x0, #+0x78",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x54",
|
||||
"sub x0, x0, #0x20 (32)",
|
||||
"tbnz x0, #63, #+0x44",
|
||||
"sub x0, x0, #0x20 (32)",
|
||||
@ -2901,11 +2903,13 @@
|
||||
"mov x2, x5",
|
||||
"add x20, x0, x2",
|
||||
"add x21, x1, x2",
|
||||
"b #+0x98",
|
||||
"cbz x0, #+0x80",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x64",
|
||||
"b #+0xa0",
|
||||
"cbz x0, #+0x88",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x64",
|
||||
"sub x1, x1, #0x1f (31)",
|
||||
"sub x2, x2, #0x1f (31)",
|
||||
"sub x0, x0, #0x20 (32)",
|
||||
@ -2945,18 +2949,20 @@
|
||||
]
|
||||
},
|
||||
"rep movsw": {
|
||||
"ExpectedInstructionCount": 79,
|
||||
"ExpectedInstructionCount": 83,
|
||||
"Comment": "0xa5",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrsb x20, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"mov x2, x10",
|
||||
"tbnz w20, #1, #+0x8c",
|
||||
"cbz x0, #+0x70",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"tbnz w20, #1, #+0x94",
|
||||
"cbz x0, #+0x78",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x54",
|
||||
"sub x0, x0, #0x10 (16)",
|
||||
"tbnz x0, #63, #+0x44",
|
||||
"sub x0, x0, #0x10 (16)",
|
||||
@ -2986,11 +2992,13 @@
|
||||
"mov x2, x5",
|
||||
"add x20, x0, x2, lsl #1",
|
||||
"add x21, x1, x2, lsl #1",
|
||||
"b #+0x98",
|
||||
"cbz x0, #+0x80",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x64",
|
||||
"b #+0xa0",
|
||||
"cbz x0, #+0x88",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x64",
|
||||
"sub x1, x1, #0x1e (30)",
|
||||
"sub x2, x2, #0x1e (30)",
|
||||
"sub x0, x0, #0x10 (16)",
|
||||
@ -3030,18 +3038,20 @@
|
||||
]
|
||||
},
|
||||
"rep movsd": {
|
||||
"ExpectedInstructionCount": 79,
|
||||
"ExpectedInstructionCount": 83,
|
||||
"Comment": "0xa5",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrsb x20, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"mov x2, x10",
|
||||
"tbnz w20, #1, #+0x8c",
|
||||
"cbz x0, #+0x70",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"tbnz w20, #1, #+0x94",
|
||||
"cbz x0, #+0x78",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x54",
|
||||
"sub x0, x0, #0x8 (8)",
|
||||
"tbnz x0, #63, #+0x44",
|
||||
"sub x0, x0, #0x8 (8)",
|
||||
@ -3071,11 +3081,13 @@
|
||||
"mov x2, x5",
|
||||
"add x20, x0, x2, lsl #2",
|
||||
"add x21, x1, x2, lsl #2",
|
||||
"b #+0x98",
|
||||
"cbz x0, #+0x80",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x64",
|
||||
"b #+0xa0",
|
||||
"cbz x0, #+0x88",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x64",
|
||||
"sub x1, x1, #0x1c (28)",
|
||||
"sub x2, x2, #0x1c (28)",
|
||||
"sub x0, x0, #0x8 (8)",
|
||||
@ -3115,18 +3127,20 @@
|
||||
]
|
||||
},
|
||||
"rep movsq": {
|
||||
"ExpectedInstructionCount": 79,
|
||||
"ExpectedInstructionCount": 83,
|
||||
"Comment": "0xa5",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrsb x20, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"mov x2, x10",
|
||||
"tbnz w20, #1, #+0x8c",
|
||||
"cbz x0, #+0x70",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"tbnz w20, #1, #+0x94",
|
||||
"cbz x0, #+0x78",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x54",
|
||||
"sub x0, x0, #0x4 (4)",
|
||||
"tbnz x0, #63, #+0x44",
|
||||
"sub x0, x0, #0x4 (4)",
|
||||
@ -3156,11 +3170,13 @@
|
||||
"mov x2, x5",
|
||||
"add x20, x0, x2, lsl #3",
|
||||
"add x21, x1, x2, lsl #3",
|
||||
"b #+0x98",
|
||||
"cbz x0, #+0x80",
|
||||
"orr x3, x1, x2",
|
||||
"and x3, x3, #0x3",
|
||||
"cbnz x3, #+0x64",
|
||||
"b #+0xa0",
|
||||
"cbz x0, #+0x88",
|
||||
"sub x3, x1, x2",
|
||||
"tbz x3, #63, #+0x8",
|
||||
"neg x3, x3",
|
||||
"sub x3, x3, #0x20 (32)",
|
||||
"tbnz x3, #63, #+0x64",
|
||||
"sub x1, x1, #0x18 (24)",
|
||||
"sub x2, x2, #0x18 (24)",
|
||||
"sub x0, x0, #0x4 (4)",
|
||||
@ -3541,17 +3557,15 @@
|
||||
]
|
||||
},
|
||||
"rep stosb": {
|
||||
"ExpectedInstructionCount": 59,
|
||||
"ExpectedInstructionCount": 55,
|
||||
"Comment": "0xaa",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxtb w20, w4",
|
||||
"ldrsb x21, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"tbnz w21, #1, #+0x6c",
|
||||
"cbz x0, #+0x60",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x4c",
|
||||
"tbnz w21, #1, #+0x64",
|
||||
"cbz x0, #+0x58",
|
||||
"sub x0, x0, #0x20 (32)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
"dup v1.16b, w20",
|
||||
@ -3574,10 +3588,8 @@
|
||||
"sub x0, x0, #0x1 (1)",
|
||||
"cbnz x0, #-0x8",
|
||||
"add x11, x11, x5",
|
||||
"b #+0x70",
|
||||
"cbz x0, #+0x68",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"b #+0x68",
|
||||
"cbz x0, #+0x60",
|
||||
"sub x1, x1, #0x1f (31)",
|
||||
"sub x0, x0, #0x20 (32)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
@ -3606,17 +3618,15 @@
|
||||
]
|
||||
},
|
||||
"rep stosw": {
|
||||
"ExpectedInstructionCount": 59,
|
||||
"ExpectedInstructionCount": 55,
|
||||
"Comment": "0xab",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"ldrsb x21, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"tbnz w21, #1, #+0x6c",
|
||||
"cbz x0, #+0x60",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x4c",
|
||||
"tbnz w21, #1, #+0x64",
|
||||
"cbz x0, #+0x58",
|
||||
"sub x0, x0, #0x10 (16)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
"dup v1.8h, w20",
|
||||
@ -3639,10 +3649,8 @@
|
||||
"sub x0, x0, #0x1 (1)",
|
||||
"cbnz x0, #-0x8",
|
||||
"add x11, x11, x5, lsl #1",
|
||||
"b #+0x70",
|
||||
"cbz x0, #+0x68",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"b #+0x68",
|
||||
"cbz x0, #+0x60",
|
||||
"sub x1, x1, #0x1e (30)",
|
||||
"sub x0, x0, #0x10 (16)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
@ -3671,17 +3679,15 @@
|
||||
]
|
||||
},
|
||||
"rep stosd": {
|
||||
"ExpectedInstructionCount": 59,
|
||||
"ExpectedInstructionCount": 55,
|
||||
"Comment": "0xab",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w4",
|
||||
"ldrsb x21, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"tbnz w21, #1, #+0x6c",
|
||||
"cbz x0, #+0x60",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x4c",
|
||||
"tbnz w21, #1, #+0x64",
|
||||
"cbz x0, #+0x58",
|
||||
"sub x0, x0, #0x8 (8)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
"dup v1.4s, w20",
|
||||
@ -3704,10 +3710,8 @@
|
||||
"sub x0, x0, #0x1 (1)",
|
||||
"cbnz x0, #-0x8",
|
||||
"add x11, x11, x5, lsl #2",
|
||||
"b #+0x70",
|
||||
"cbz x0, #+0x68",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"b #+0x68",
|
||||
"cbz x0, #+0x60",
|
||||
"sub x1, x1, #0x1c (28)",
|
||||
"sub x0, x0, #0x8 (8)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
@ -3736,7 +3740,7 @@
|
||||
]
|
||||
},
|
||||
"rep stosq": {
|
||||
"ExpectedInstructionCount": 58,
|
||||
"ExpectedInstructionCount": 54,
|
||||
"Comment": [
|
||||
"Unrolling the loop for faster memset can be done.",
|
||||
"Taking advantage of ARM MOPs instructions can be done",
|
||||
@ -3746,10 +3750,8 @@
|
||||
"ldrsb x20, [x28, #714]",
|
||||
"mov x0, x5",
|
||||
"mov x1, x11",
|
||||
"tbnz w20, #1, #+0x6c",
|
||||
"cbz x0, #+0x60",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x4c",
|
||||
"tbnz w20, #1, #+0x64",
|
||||
"cbz x0, #+0x58",
|
||||
"sub x0, x0, #0x4 (4)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
"dup v1.2d, x4",
|
||||
@ -3772,10 +3774,8 @@
|
||||
"sub x0, x0, #0x1 (1)",
|
||||
"cbnz x0, #-0x8",
|
||||
"add x11, x11, x5, lsl #3",
|
||||
"b #+0x70",
|
||||
"cbz x0, #+0x68",
|
||||
"and x3, x1, #0x3",
|
||||
"cbnz x3, #+0x54",
|
||||
"b #+0x68",
|
||||
"cbz x0, #+0x60",
|
||||
"sub x1, x1, #0x18 (24)",
|
||||
"sub x0, x0, #0x4 (4)",
|
||||
"tbnz x0, #63, #+0x3c",
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user