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OpcodeDispatcher: Handle VPSRLD (immediate)

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This commit is contained in:
lioncash 2022-12-20 19:08:56 +00:00
parent 666f8bfbd9
commit 133a644231
4 changed files with 51 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -6049,6 +6049,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b110), 1, &OpDispatchBuilder::VPSLLIOp<2>},
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b100), 1, &OpDispatchBuilder::VPSRAIOp<2>},
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b010), 1, &OpDispatchBuilder::VPSRLIOp<4>},
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b110), 1, &OpDispatchBuilder::VPSLLIOp<4>},
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b100), 1, &OpDispatchBuilder::VPSRAIOp<4>},

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
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@ -1357,6 +1357,8 @@ void OpDispatchBuilder::VPSRLIOp(OpcodeArgs) {
template
void OpDispatchBuilder::VPSRLIOp<2>(OpcodeArgs);
template
void OpDispatchBuilder::VPSRLIOp<4>(OpcodeArgs);
OrderedNode* OpDispatchBuilder::PSLLIImpl(OpcodeArgs, size_t ElementSize,
OrderedNode *Src, uint64_t Shift) {

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -492,7 +492,7 @@ void InitializeVEXTables() {
{OPD(TYPE_VEX_GROUP_12, 1, 0b100), 1, X86InstInfo{"VPSRAW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_12, 1, 0b110), 1, X86InstInfo{"VPSLLW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_13, 1, 0b010), 1, X86InstInfo{"VPSRLD", TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
{OPD(TYPE_VEX_GROUP_13, 1, 0b010), 1, X86InstInfo{"VPSRLD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_13, 1, 0b100), 1, X86InstInfo{"VPSRAD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_13, 1, 0b110), 1, X86InstInfo{"VPSLLD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},

47
unittests/ASM/VEX/vpsrld_imm.asm Normal file
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@ -0,0 +1,47 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM2": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x0000616200006566", "0x0000717200007576", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x0041424300454647", "0x0051525300555657", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0x30B131B232B333B4", "0x38B939BA3ABB3BBC", "0x0000000000000000", "0x0000000000000000"],
"XMM6": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0x0000616200006566", "0x0000717200007576", "0x0000616200006566", "0x0000717200007576"],
"XMM8": ["0x0041424300454647", "0x0051525300555657", "0x0041424300454647", "0x0051525300555657"],
"XMM9": ["0x30B131B232B333B4", "0x38B939BA3ABB3BBC", "0x30B131B232B333B4", "0x38B939BA3ABB3BBC"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rdx]
vmovapd ymm1, [rdx + 32]
vpsrld xmm2, xmm0, 32
vpsrld xmm3, xmm1, 16
vpsrld xmm4, xmm0, 8
vpsrld xmm5, xmm1, 1
vpsrld ymm6, ymm0, 32
vpsrld ymm7, ymm1, 16
vpsrld ymm8, ymm0, 8
vpsrld ymm9, ymm1, 1
hlt
align 32
.data:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x6162636465666768
dq 0x7172737475767778
dq 0x6162636465666768
dq 0x7172737475767778