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OpcodeDispatcher: Handle VPOR

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This commit is contained in:
lioncash 2022-11-29 18:42:23 +00:00
parent ef368ceafa
commit 16ed20cfae
3 changed files with 48 additions and 2 deletions
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3
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5851,8 +5851,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b01, 0xD6), 1, &OpDispatchBuilder::MOVQOp},
{OPD(1, 0b01, 0xD7), 1, &OpDispatchBuilder::UnimplementedOp},
{OPD(1, 0b01, 0xEB), 1, &OpDispatchBuilder::UnimplementedOp},
{OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::VMOVVectorNTOp},
{OPD(1, 0b01, 0xEB), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VOR, 16>},
{OPD(1, 0b01, 0xEF), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VXOR, 16>},
{OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp},

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -235,7 +235,7 @@ void InitializeVEXTables() {
{OPD(1, 0b01, 0xE8), 1, X86InstInfo{"VPSUBSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xE9), 1, X86InstInfo{"VPSUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xEA), 1, X86InstInfo{"VPMINSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xEB), 1, X86InstInfo{"VPOR", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xEB), 1, X86InstInfo{"VPOR", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xEC), 1, X86InstInfo{"VPADDSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xED), 1, X86InstInfo{"VPADDSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xEE), 1, X86InstInfo{"VPMAXSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

45
unittests/ASM/VEX/vpor.asm Normal file
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@ -0,0 +1,45 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x4142434445464748", "0x5152535455565758", "0x6162636465666768", "0x7172737475767778"],
"XMM1": ["0xCCCCCCCC75767778", "0x61626364DDDDDDDD", "0xEEEEEEEE55565758", "0x41424344FFFFFFFF"],
"XMM2": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
"XMM3": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
"XMM5": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data1]
lea rbx, [rel .data2]
vmovapd ymm0, [rdx]
vmovapd ymm1, [rbx]
; Register only
vpor ymm2, ymm0, ymm1
vpor xmm3, xmm0, xmm1
; With memory operand
vpor ymm4, ymm0, [rbx]
vpor xmm5, xmm0, [rbx]
hlt
align 32
.data1:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x6162636465666768
dq 0x7172737475767778
.data2:
dq 0xCCCCCCCC75767778
dq 0x61626364DDDDDDDD
dq 0xEEEEEEEE55565758
dq 0x41424344FFFFFFFF