From 17b851d4f37452ffc88f187206157c0b2fb7490d Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Mon, 28 Oct 2024 01:15:47 -0700
Subject: [PATCH] IR: Change VFNMLA to use IR::OpSize

---
 FEXCore/Source/Interface/IR/IR.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 2df4450ef..5c2f453a6 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -2504,7 +2504,7 @@
         "NumElements": "RegisterSize / ElementSize",
         "TiedSource": 2
       },
-      "FPR = VFNMLA u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
+      "FPR = VFNMLA OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
         "Desc": [
           "Dest = (-Vector1 * Vector2) + Addend",
           "This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."