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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-08-20 21:01:08 -04:00
parent 5d613e8716
commit 19010491da
5 changed files with 63 additions and 87 deletions
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40
unittests/InstructionCountCI/FlagM/FlagOpts.json
View File

@ -68,7 +68,7 @@
]
},
"ADC dead": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"x86Insts": [
"add rax, rbx",
"adc rcx, rcx",
@ -77,8 +77,7 @@
"ExpectedArm64ASM": [
"adds x4, x4, x6",
"adc x7, x7, x7",
"ands x26, x7, x7",
"cfinv"
"subs x26, x7, #0x0 (0)"
]
},
"INC consumed": {
@ -173,9 +172,9 @@
"uxtb w20, w4",
"sub w20, w20, #0x1 (1)",
"bfxil x4, x20, #0, #8",
"mov x26, x4",
"cmn wzr, w26, lsl #24",
"cfinv"
"cmn wzr, w4, lsl #24",
"cfinv",
"mov x26, x4"
]
},
"Variable shift dead": {
@ -227,9 +226,9 @@
"cmp x4, x6",
"cset x20, eq",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
"cmn wzr, w7, lsl #24",
"cfinv",
"mov x26, x7"
]
},
"Partial NZCV select (add)": {
@ -243,9 +242,9 @@
"adds x4, x4, x6",
"cset x20, eq",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
"cmn wzr, w7, lsl #24",
"cfinv",
"mov x26, x7"
]
},
"AND use only ZF": {
@ -259,9 +258,9 @@
"ands w4, w4, w6",
"cset x20, eq",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
"cmn wzr, w7, lsl #24",
"cfinv",
"mov x26, x7"
]
},
"AND use only PF": {
@ -279,13 +278,13 @@
"eon w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
"cmn wzr, w7, lsl #24",
"cfinv",
"mov x26, x7"
]
},
"Dead cmpxchg flags": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"x86Insts": [
"cmpxchg8b [rbp]",
"test rax, rax"
@ -300,8 +299,7 @@
"rmif x0, #0, #NzCV",
"csel x4, x20, x4, ne",
"csel x5, x21, x5, ne",
"ands x26, x4, x4",
"cfinv"
"subs x26, x4, #0x0 (0)"
]
}
}

22
unittests/InstructionCountCI/FlagM/Primary.json
View File

@ -2204,34 +2204,32 @@
"ExpectedInstructionCount": 3,
"Comment": "0xa8",
"ExpectedArm64ASM": [
"mov x26, x4",
"cmn wzr, w26, lsl #24",
"cfinv"
"cmn wzr, w4, lsl #24",
"cfinv",
"mov x26, x4"
]
},
"test ax, -1": {
"ExpectedInstructionCount": 3,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"mov x26, x4",
"cmn wzr, w26, lsl #16",
"cfinv"
"cmn wzr, w4, lsl #16",
"cfinv",
"mov x26, x4"
]
},
"test eax, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"ands w26, w4, w4",
"cfinv"
"subs w26, w4, #0x0 (0)"
]
},
"test rax, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"ands x26, x4, x4",
"cfinv"
"subs x26, x4, #0x0 (0)"
]
},
"scasb": {

16
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

@ -2240,25 +2240,23 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x26, x6",
"cmn wzr, w26, lsl #16",
"cfinv"
"cmn wzr, w6, lsl #16",
"cfinv",
"mov x26, x6"
]
},
"test ebx, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w6, w6",
"cfinv"
"subs w26, w6, #0x0 (0)"
]
},
"test rbx, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x6, x6",
"cfinv"
"subs x26, x6, #0x0 (0)"
]
},
"neg bx": {

52
unittests/InstructionCountCI/Primary.json
View File

@ -1960,42 +1960,36 @@
"ExpectedInstructionCount": 5,
"Comment": "0x84",
"ExpectedArm64ASM": [
"mov x26, x4",
"cmn wzr, w26, lsl #24",
"cmn wzr, w4, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x26, x4"
]
},
"test ax, ax": {
"ExpectedInstructionCount": 5,
"Comment": "0x84",
"ExpectedArm64ASM": [
"mov x26, x4",
"cmn wzr, w26, lsl #16",
"cmn wzr, w4, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x26, x4"
]
},
"test eax, eax": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 1,
"Comment": "0x84",
"ExpectedArm64ASM": [
"ands w26, w4, w4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w4, #0x0 (0)"
]
},
"test rax, rax": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 1,
"Comment": "0x84",
"ExpectedArm64ASM": [
"ands x26, x4, x4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs x26, x4, #0x0 (0)"
]
},
"xchg bl, cl": {
@ -3588,42 +3582,36 @@
"ExpectedInstructionCount": 5,
"Comment": "0xa8",
"ExpectedArm64ASM": [
"mov x26, x4",
"cmn wzr, w26, lsl #24",
"cmn wzr, w4, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x26, x4"
]
},
"test ax, -1": {
"ExpectedInstructionCount": 5,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"mov x26, x4",
"cmn wzr, w26, lsl #16",
"cmn wzr, w4, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x26, x4"
]
},
"test eax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"ands w26, w4, w4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w4, #0x0 (0)"
]
},
"test rax, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"ands x26, x4, x4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs x26, x4, #0x0 (0)"
]
},
"stosb": {

20
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -2636,31 +2636,25 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x26, x6",
"cmn wzr, w26, lsl #16",
"cmn wzr, w6, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x26, x6"
]
},
"test ebx, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w6, w6",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w6, #0x0 (0)"
]
},
"test rbx, -1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x6, x6",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs x26, x6, #0x0 (0)"
]
},
"not bx": {